SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND APPARATUS FOR DESIGNING SAME

• US 20100123480A1
• Filed: 01/22/2010
• Published: 05/20/2010
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: KIMURA, Takahiro, KITADA, Hideki
• Granted Patent: US 8,319,277 B2
• Time in Patent Office: Days
• US Class Current: 326/93
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device that includes multiple logic circuit cells having respective logic circuits formed therein and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.

Claims

1. A semiconductor device, comprising:

a plurality of logic circuit cells having respective logic circuits formed therein; and

a plurality of interconnects connected to the corresponding logic circuit cells,

wherein at least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of opening ratios of the remaining interconnects.

2. The semiconductor device as claimed in claim 1, wherein the logic circuit cells include a clock signal generator cell and a plurality of clock-signal-distributed cells to which a clock signal is distributed from the clock signal generator cell, and

the interconnects are clock signal distribution lines connecting the clock signal generator cell and the clock-signal-distributed cells.

3. The semiconductor device as claimed in claim 2, wherein the opening ratios are determined differently in accordance with a difference between lengths of the clock signal distribution lines.

4. The semiconductor device as claimed in claim 3, wherein a shorter one of the clock signal distribution lines has the opening ratio greater than the opening ratio of a longer one of the clock signal distribution lines based on a comparison between the lengths of the clock signal distribution lines.

5. The semiconductor device as claimed in claim 2, wherein the opening ratios are determined differently in accordance with a difference between heights of the clock signal distribution lines.

6. The semiconductor device as claimed in claim 5, wherein a higher one of the clock signal distribution lines has the opening ratio greater than the opening ratio of a lower one of the clock signal distribution lines based on a comparison between the heights of the clock signal distribution lines.

7. The semiconductor device as claimed in claim 1, wherein the opening has a slit shape.

8. The semiconductor device as claimed in claim 7, wherein the slit shape divides a predetermined region of the at least one of the interconnects into a plurality of portions.

9. The semiconductor device as claimed in claim 1, wherein the opening has a dot shape.