SEMICONDUCTOR DEVICE AND INSPECTION METHOD OF SEMICONDUCTOR DEVICE AND WIRELESS CHIP

• US 20100123555A1
• Filed: 01/25/2010
• Published: 05/20/2010
• Est. Priority Date: 08/05/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: DEMBO, Hiroki
• Granted Patent: US 7,937,636 B2
• Time in Patent Office: Days
• US Class Current: 340/10.100
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926

Abstract

The invention provides an inspection method of a semiconductor device which receives a test program wirelessly. As an inspection method of the semiconductor device, a test program is transmitted as a communication signal for every test. By transmitting a test program as a communication signal wirelessly in the case of an operation test, test contents are changed as required. As a result, a test program can be easily changed and an inspection circuit or the like is not required. In this manner, manufacturing cost of a wireless chip can be reduced.

Claims

1. A semiconductor device comprising:

an RF circuit for receiving a reception signal and transmitting a transmission signal by wireless communication, the RF circuit comprising an antenna, a resonant circuit, a power source circuit, a reset circuit, a clock circuit, a demodulation circuit, and a modulation circuit;

a reception circuit for extracting SOF, reception data, and EOF from a signal demodulated by the demodulation circuit;

a data storing portion comprising a memory which stores the reception data; and

a liquid crystal driver portion operationally connected with the date storing portion.

2. A semiconductor device according to claim 1 wherein the SOF is Start OF Frame.

3. A semiconductor device according to claim 1 wherein the EOF is End Of Frame.

4. A semiconductor device according to claim 1 wherein the demodulation circuit comprises a low pass filter.

5. A semiconductor device according to claim 1 wherein the data storing portion further comprises a control register, a reception data register, and a transmission data register.

6. A semiconductor device according to claim 1 wherein the memory of the data storing portion comprises a read only memory.

7. A semiconductor device according to claim 1 wherein the memory of the data storing portion comprises a random access memory.

8. A semiconductor device according to claim 1 wherein the memory of the data storing portion comprises a mask read only memory.

9. A semiconductor device according to claim 1 wherein the memory of the data storing portion comprises a static random access memory.

10. A semiconductor device comprising:

an RF circuit for receiving a reception signal and transmitting a transmission signal by wireless communication, the RF circuit comprising an antenna, a resonant circuit, a power source circuit, a reset circuit, a clock circuit, a demodulation circuit, and a modulation circuit;

a reception circuit for extracting SOF, reception data, and EOF from a signal demodulated by the demodulation circuit;

a data storing portion comprising a memory which stores the reception data;

a liquid crystal driver portion operationally connected with the date storing portion and comprises a substrate, a pixel electrode provided over the substrate, a liquid crystal molecule provided over the pixel electrode, and a counter electrode provided over the liquid crystal molecule; and

an arithmetic circuit for controlling the liquid crystal molecule, the arithmetic circuit operationally connected with the data storing portion.

11. A semiconductor device according to claim 10 wherein the SOF is Start Of Frame.

12. A semiconductor device according to claim 10 wherein the EOF is End Of Frame.

13. A semiconductor device according to claim 10 wherein the demodulation circuit comprises a low pass filter.

14. A semiconductor device according to claim 10 wherein the data storing portion further comprises a control register, a reception data register, and a transmission data register.

15. A semiconductor device according to claim 10 wherein the memory of the data storing portion comprises a read only memory.

16. A semiconductor device according to claim 10 wherein the memory of the data storing portion comprises a random access memory.

17. A semiconductor device according to claim 10 wherein the memory of the data storing portion comprises a mask read only memory.

18. A semiconductor device according to claim 10 wherein the memory of the data storing portion comprises a static random access memory.