STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N

• US 20100124088A1
• Filed: 11/15/2009
• Published: 05/20/2010
• Est. Priority Date: 11/16/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Perlmutter, Uri, Sokolov, Dotan, Sommer, Naftali
• Granted Patent: US 8,208,304 B2
• Time in Patent Office: Days
• US Class Current: 365/45
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.

Claims

1. A method for data storage, comprising:

accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands, each of which programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells; and

programming the subset of the memory cells to store M pages of the data, M>

N, by performing a sequence of the programming commands drawn only from the set.

2. The method according to claim 1, wherein the memory further supports a list of built-in read commands, each of which read commands reads a respective one of the group of the N pages, and comprising reading the M pages from the subset of the memory cells by performing a series of read commands drawn only from the list.

3. The method according to claim 2, wherein performing the series of the read commands comprises notifying the memory of one or more read threshold values to be applied in at least one of the read commands in the series.

4. The method according to claim 1, wherein programming the subset of the memory cells comprises caching the data in the memory in no more than N page buffers.

5. The method according to claim 1, wherein programming the subset of the memory cells comprises notifying the memory of one or more programming threshold values to be applied in at least one of the programming commands in the sequence.

6. The method according to claim 1, wherein programming the subset of the memory cells comprises applying a series of programming pulses to the memory cells in the subset, and notifying the memory of a characteristic of the programming pulses to be applied during at least one of the programming commands in the sequence.

7. The method according to claim 1, wherein a given programming command in the sequence involves reading a previously-programmed page from the subset of the memory cells using one or more read thresholds, and wherein programming the subset of the memory cells comprises notifying the memory of respective values of the one or more read thresholds.

8. The method according to claim 1, wherein programming the subset of the memory cells comprises, during a given programming command in the sequence, modifying respective storage values of only some of the memory cells in the subset by programming the other memory cells in the subset with respective data values that cause their storage values to remain unchanged by the given programming command.

9. The method according to claim 1, and comprising configuring the memory to operate in one of first and second operational modes, wherein programming the subset of the memory cells comprises storing a maximum of M pages in the subset of the memory cells when operating in the first operational mode, and storing a maximum of N pages in the subset of the memory cells when operating in the second operational mode.

10. A data storage apparatus, comprising:

an interface for communicating with a memory that includes multiple analog memory cells and supports a set of built-in programming commands, each of which programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells; and

a processor, which is configured to accept data for storage in the memory, and to program the subset of the memory cells to store M pages of the data, M>

N, by performing a sequence of the programming commands drawn only from the set.

11. The apparatus according to claim 10, wherein the memory further supports a list of built-in read commands, each of which read commands reads a respective one of the group of the N pages, and wherein the processor is configured to read the M pages from the subset of the memory cells by performing a series of read commands drawn only from the list.

12. The apparatus according to claim 11, wherein the processor is configured to notify the memory of one or more read threshold values to be applied in at least one of the read commands in the series.

13. The apparatus according to claim 10, wherein the processor is configured to cache the data in the memory in no more than N page buffers when programming the subset of the memory cells.

14. The apparatus according to claim 10, wherein the processor is configured to notify the memory of one or more programming threshold values to be applied in at least one of the programming commands in the sequence.

15. The apparatus according to claim 10, wherein the memory device programs the subset of the memory cells by applying a series of programming pulses to the memory cells in the subset, and wherein the processor is configured to notify the memory of a characteristic of the programming pulses to be applied during at least one of the programming commands in the sequence.

16. The apparatus according to claim 10, wherein a given programming command in the sequence involves reading a previously-programmed page from the subset of the memory cells using one or more read thresholds, and wherein the processor is configured to notify the memory of respective values of the one or more read thresholds.

17. The apparatus according to claim 10, wherein the processor is configured to modify, during a given programming command in the sequence, respective storage values of only some of the memory cells in the subset by programming the other memory cells in the subset with respective data values that cause their storage values to remain unchanged by the given programming command.

18. The apparatus according to claim 10, wherein the memory is configurable to operate in one of first and second operational modes, wherein a maximum of M pages is stored in the subset when operating in the first operational mode, and a maximum of N pages is stored in the subset when operating in the second operational mode.

19. A data storage apparatus, comprising:

a memory, which comprises multiple analog memory cells and supports a set of built-in programming commands, each of which programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells; and

a processor, which is configured to accept data for storage in the memory, and to program the subset of the memory cells to store M pages of the data, M>

N, by performing a sequence of the programming commands drawn only from the set.

20. The apparatus according to claim 19, wherein the memory further supports a list of built-in read commands, each of which read commands reads a respective one of the group of the N pages, and wherein the processor is configured to read the M pages from the subset of the memory cells by performing a series of read commands drawn only from the list.

21. The apparatus according to claim 19, wherein the memory comprises K page buffers, K≦

N, and is configured to cache the data in the K page buffers when programming the subset of the memory cells.

22. A method for data storage, comprising:

accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands for programming the memory cells to a first number of programming states; and

programming the memory cells to a second number of programming states, which is less than the first number and is not an integer power of two, by performing a sequence of the programming commands drawn only from the set.

23. A method for data storage, comprising:

accepting a request to retrieve data from a memory, which includes multiple analog memory cells, holds M pages of the data in a subset of the memory cells, and supports a list of built-in read commands, each of which read commands reads a respective one of N pages, N<

M; and

responsively to the request, reading the M pages from the subset of the memory cells by performing a series of read commands drawn only from the list.

24. The method according to claim 23, wherein performing the series of the read commands comprises notifying the memory of one or more read threshold values to be applied in at least one of the read commands in the series.