Self-Aligned Three-Dimensional Non-Volatile Memory Fabrication

• US 20100124813A1
• Filed: 05/19/2009
• Published: 05/20/2010
• Est. Priority Date: 11/18/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Purayath, Vinod R, Scheuerlein, Roy E., Kai, James K., Chien, Henry, Ping, Er-Xuan, Orimoto, Takashi, Matamis, George
• Granted Patent: US 8,105,867 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 21/20 Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

Claims

1. A method of fabricating non-volatile storage, comprising:

forming over a substrate a first conductor elongated in a first direction, the first conductor having sidewalls elongated in the first direction;

forming a second conductor elongated in a second direction that is substantially perpendicular to the first direction, the second conductor being vertically-separated from the first conductor and having sidewalls elongated in the second direction;

forming a third conductor elongated in the first direction, the third conductor being vertically-separated from the first conductor and the second conductor and having sidewalls elongated in the first direction;

forming a first pillar between the first conductor and the second conductor, the first pillar having first sidewalls elongated in the first direction and second sidewalls elongated in the second direction, the second sidewalls of the first pillar being self-aligned with at least a first portion of the sidewalls of the second conductor, the first pillar including a steering element and at least one state change element; and

forming a second pillar between the second conductor and the third conductor, the second pillar having first sidewalls elongated in the first direction and second sidewalls elongated in the second direction, the second sidewalls of the second pillar being self-aligned with at least a second portion of the sidewalls of the second conductor, the second pillar including a steering element and at least one state change element, the second portion of the sidewalls of the second conductor being misaligned with the first portion of the sidewalls of the second conductor.

2. A method according to claim 1, wherein forming the second conductor includes:

depositing a first metal layer and applying a first pattern having repeating features in the first direction;

etching the first metal layer according to the first pattern to define the at least a first portion of the sidewalls of the second conductor;

depositing a second metal layer and applying a second patterning having repeating features in the first direction; and

etching the second metal layer according to the second pattern to define the at least a second portion of the sidewalls of the second conductor.

3. A method according to claim 1, wherein:

the first sidewalls of the first pillar are self-aligned with the sidewalls of the first conductor; and

the first sidewalls of the second pillar are self-aligned with the sidewalls of the third conductor.

4. A method according to claim 3, wherein:

the second conductor includes a first strip of conductive material and a second strip of conductive material, the first strip of conductive material forming the first portion of the sidewalls of the second conductor and the second strip of conductive material forming the second portion of the sidewalls of the second conductor;

forming the second conductor includes etching a first layer of conducive material into the first strip of conductive material using a first pattern and etching a second layer of conductive material into the second strip of conductive material using a second pattern;

forming the first pillar includes etching a layer stack into the first pillar using the first pattern, wherein etching the first layer of conductive material and the layer stack using the first pattern defines the second sidewalls of the first pillar and the first portion of the sidewalls of the second conductor; and

forming the second pillar includes etching a second layer stack into the second pillar using the second pattern, wherein etching the second layer of conductive material and the second layer stack using the second pattern defines the second sidewalls of the second pillar and the second portion of the sidewalls of the second conductor.

5. A method according to claim 1, wherein:

the state change element in the first pillar is a diode;

the state change element in the second pillar is a diode;

the at least one state change element in the first pillar is a re-writable phase change element; and

the at least one state change element in the second pillar is a re-writable phase change element.

6. A method according to claim 1, wherein:

the state change element in the first pillar is a diode;

the state change element in the second pillar is a diode;

the at least one state change element in the first pillar is an anti-fuse; and

the at least one state change element in the second pillar is an anti-fuse.

7. A method performed as part of non-volatile memory fabrication, comprising:

forming a first layer stack elongated in a first direction over a substrate, the first layer stack including a first strip of conductive material and a plurality of strips of semiconductor material;

forming a second layer of conductive material over the first layer stack;

etching the second layer of conductive material and the plurality of strips of semiconductor material using a first pattern, said etching includes etching the second layer of conductive material into a second strip of conductive material elongated in a second direction that is substantially orthogonal to the first direction and etching the plurality of strips of semiconductor material into a pillar, the pillar including first sidewalls elongated in the first direction and second sidewalls elongated in the second direction, the second sidewalls being self-aligned with sidewalls of the second strip of conductive material that are elongated in the second direction;

forming a third layer of conductive material over and in electrical contact with the second strip of conductive material after etching the second layer of conductive material and the plurality of strips of semiconductor material;

forming a set of semiconductor layers over the third layer of conductive material; and

etching the set of semiconductor layers and the third layer of conductive material using a second pattern, said etching includes etching the set of semiconductor layers into a second plurality of strips of semiconductor material elongated in the second direction and etching the third layer of conductive material into a third strip of conductive material elongated in the second direction, the third strip of conductive material including sidewalls elongated in the second direction that are self-aligned with sidewalls of the second plurality of strips of semiconductor material that are elongated in the second direction.

8. A method according to claim 7, further comprising:

forming a strip of phase change material over the first layer stack using a damascene process prior to forming the second layer of conductive material;

wherein etching the second layer of conductive material and the plurality of strips of semiconductor material using the first pattern includes etching the strip of phase change material using the first pattern such that the pillar includes a phase change region.

9. A method according to claim 7, wherein:

the set of semiconductor layers is a second set of semiconductor layers;

forming the first layer stack includes;

depositing a first set of semiconductor layers, a first conductive layer, and a state change layer, and p1 etching, according to a third pattern, the first set of semiconductor layers into the plurality of strips of semiconductor material, the first conductive layer into the first strip of conductive material, and the state change layer into a strip of state change material; and

etching the second layer of conductive material and the plurality of strips of semiconductor material using the first pattern includes etching the strip of state change material such that the pillar includes a phase change region.

10. A method according to claim 7, wherein the pillar includes:

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type;

an intrinsic region separating the first semiconductor region from the second semiconductor region, wherein the first semiconductor region, the second semiconductor region and the intrinsic region forming a diode; and

a state change region in series with the diode.

11. A method according to claim 10, wherein:

the state change region is a re-writable resistance change element.

12. A method according to claim 10, wherein:

the state change region is an antifuse.

13. A method according to claim 7, further comprising:

forming a fourth layer of conductive material over the second plurality of strips of semiconductor material; and

etching the fourth layer of conductive material and the second plurality of strips of semiconductor material using a third pattern, said etching includes etching the fourth layer of conductive material into a fourth strip of conductive material elongated in the first direction and etching the second plurality of strips of semiconductor material into a second pillar, the second pillar including first sidewalls elongated in the first direction and second sidewalls elongated in the second direction, the first sidewalls being self-aligned with sidewalls of the fourth strip of conductive material that are elongated in the first direction, the second sidewalls being self-aligned with the sidewalls of the third strip of conductive material.

14. A method of fabricating a three-dimensional non-volatile memory system, comprising:

forming a first layer of conductive material;

forming a first set of semiconductor layers over the first layer of conductive material;

etching the set of semiconductor layers and the first layer of conductive material in a second direction, thereby forming a first plurality of layer stacks elongated in a first direction substantially orthogonal to the second direction, the first plurality of layer stacks including a first set of conductors formed from the first layer of conductive material;

forming a second layer of conductive material over the plurality of layer stacks;

etching the second layer of conductive material and the first plurality of layer stacks in the first direction, thereby forming a first plurality of pillars from the first set of semiconductor layers in each layer stack and a plurality of strips of the second layer of conductive material, the plurality of strips elongated in the second direction;

forming a third layer of conductive material over the plurality of strips of the second layer of conductive material;

forming a second set of semiconductor layers over the third layer of conductive material; and

etching the second set of semiconductor layers and the third layer of conductive material in the first direction, thereby forming a second plurality of layer stacks elongated in the second direction, the second plurality of layer stacks including a plurality of strips of the third layer of conductive material elongated in the second direction, the plurality of strips of the third layer of conductive material and the plurality of strips of the second layer of conductive material being electrically connected to form a second set of conductors elongated in the second direction.

15. A method according to claim 14, wherein:

the first plurality of pillars each include a diode and a state change element;

etching the first plurality of layers stacks includes etching less than all the layers in each layer stack, each layer stack including a first strip of semiconductor material forming a first electrode for the diode in each pillar of the first plurality of pillars and a second strip of semiconductor material forming at least a portion of an intrinsic region for the diode in each pillar;

the method further comprising programming the state change element in a particular pillar by transitioning a corresponding conductor in the first set of conductors to its selected bias level prior to transitioning a corresponding conductor in the second set of conductors to its selected bias level and transitioning the corresponding conductor in the second of conductors back to its unselected bias level prior to transitioning the corresponding conductor in the first set of conductor back to is unselected bias level.

16. A method according to claim 14, wherein the first plurality of layer stacks include sacrificial strips over their upper surface, the method further comprising:

depositing an insulating material in spaces between layer stacks of the first plurality adjacent in the second direction;

removing the sacrificial strips;

slimming portions of the insulating material at a vertical height above the first plurality of layer stacks; and

depositing a phase change material in spaces between the slimmed portions of the insulating material.

17. A method according to claim 14, wherein the first set of semiconductor layers includes a layer of phase change material.

18. A method according to claim 17, wherein the first set of semiconductor layers includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type; and

an intrinsic layer separating the first semiconductor layer from the second semiconductor layer.

19. A method according to claim 18, wherein each pillar in the first plurality includes:

a diode having a first electrode formed from the first semiconductor layer and a second electrode formed from the second semiconductor layer;

a state change element formed from the layer of phase change material, the state change element in series with the diode.

20. A method according to claim 14, further comprising:

forming a fourth layer of conductive material over the second plurality of layer stacks;

etching the fourth layer of conductive material and the second plurality of layer stacks in the second direction, thereby forming a second plurality of pillars from the second set of semiconductor layers in each layer stack of the second plurality and a plurality of strips of the fourth layer of conductive material, the plurality of strips of the fourth layer of conductive material elongated in the first direction.

21. A method of non-volatile memory fabrication, comprising:

forming a first set of conductors elongated in a first direction over a substrate;

forming a first set semiconductor layer stack lines over the first set of conductors;

forming a first layer of silicon over the first set of semiconductor layer stack lines;

etching the first layer of silicon and the first set of semiconductor layer stack lines according to a first pattern, said etching forming from the first layer of silicon a second set of conductors elongated in a second direction substantially orthogonal to the first direction, said etching forming from the first set of semiconductor layer stack lines a first plurality of pillars at intersections of the first set of conductors and the second set of conductors; and

silicidizing the second set of conductor after etching the first layer of silicon to form silicide conductors for the second set.

22. A method according to claim 21, further comprising:

forming a second semiconductor layer stack over the second set of conductors after silicidizing;

etching the second semiconductor layer stack according to a second pattern to form a second set of semiconductor layer stack lines elongated in the second direction, the first pattern and the second pattern having repeating features in the first direction;

forming a second layer of silicon over the second set of semiconductor layer stack lines; and

etching the second layer of silicon and the second set of semiconductor layer stack lines according to a third pattern having repeating features in the second direction, said etching forming from the second layer of silicon a third set of conductors elongated in the first direction and forming from the second set of semiconductor layer stack lines a second plurality of pillars at intersections of the second set of conductors and the first set of conductors.

23. A method according to claim 21, wherein silicidizing the first layer of silicon comprises:

forming a surface layer of metal on the first set of conductors; and

thermally annealing the surface layer of metal and the first set of conductors to form silicide conductors for the first set.