COMPACT TEST CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME
First Claim
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1. A test circuit, comprising:
- a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items; and
a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals.
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Abstract
A compact test circuit prevents a chip area increase by reducing the number of global lines, i.e., transmission paths of test mode item signals. The test circuit is capable of reducing a test time by performing several tests in parallel through one test mode item signal. The test circuit includes a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items, and a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals.
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Citations
34 Claims
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1. A test circuit, comprising:
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a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items; and a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit, comprising:
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a test mode item signal generating block configured to generate a test mode item signal corresponding to a test mode item; a coding block configured to code the test mode item signal to generate first and second test control signals; and first and second internal circuits configured to be test-driven concurrently in response to the corresponding first and second test signals and having no cross-circuit effect. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An integrated circuit, comprising:
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a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items in response to an input signal applied through a global line; a coding block configured to receive the plurality of test mode item signals through a first local line and code the plurality of test mode item signals to generate multiple test control signals per each of the test mode item signals; and a multiplicity of internal circuits configured to receive the multiplicity of test control signals through a second local line, and to be test-driven in response to the corresponding test control signal, wherein at least two internal circuits are configured to be test-driven concurrently. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method for testing an internal circuit of an integrated circuit, the method comprising:
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generating a test mode item signal corresponding to a test mode item; coding the test mode item signal to generate at least two test control signals; and test-driving at least two internal circuit blocks concurrently by using the test control signals. - View Dependent Claims (32, 33, 34)
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Specification