COMPACT TEST CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME

• US 20100125431A1
• Filed: 04/22/2009
• Published: 05/20/2010
• Est. Priority Date: 11/17/2008
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: SEO, Woo-Hyun
• Application Number:
  US12/427,901
• Publication Number:
  US 20100125431A1
• Time in Patent Office: Days
• US Class Current: 702/120
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

A compact test circuit prevents a chip area increase by reducing the number of global lines, i.e., transmission paths of test mode item signals. The test circuit is capable of reducing a test time by performing several tests in parallel through one test mode item signal. The test circuit includes a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items, and a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals.

Claims

1. A test circuit, comprising:

a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items; and

a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals.

2. The test circuit of claim 1, wherein the test mode item signal generating block activates the plurality of test mode item signals sequentially.

3. The test circuit of claim 1, wherein the coding block includes a plurality of coding units, each including:

a first path configured to pass the test mode item signal to be outputted as a first test control signal; and

a second path configured to invert the test mode item signal to generate a second test control signal.

4. The test circuit of claim 1, further comprising:

a test mode entry controlling block configured to generate a test mode entry signal to provide the test mode entry signal to the test mode item signal generating block.

5. The test circuit of claim 4, wherein the test mode entry controlling block is configured to generate a pulse signal toggled based on a test address and output the pulse signal to the test mode item signal generating block.

6. The test circuit of claim 5, wherein the test mode item signal generating block is configured to sequentially latch the test mode entry signal by a predetermined time interval in response to the pulse signal in order to output the test mode item signals.

7. The test circuit of claim 5, wherein the test mode item signal generating block includes:

a plurality of shift registers connected in series, the shift registers being configured to output the test mode item signals sequentially,

wherein the shift register of a first stage is configured to latch the test mode entry signal in response to the pulse signal, and the shift registers of the next stage are configured to latch an output of the shift register of the previous stage in response to the pulse signal.

8. The test circuit of claim 1, wherein the test mode item signal generating block is configured to be reset by a reset signal.

9. The test circuit of claim 5, wherein the test mode entry signal and the pulse signal are configured to be transferred to the test mode item signal generating block through a global line.

10. The test circuit of claim 1, wherein the test mode item signal and the test control signal are configured to be transferred through a local line.

11. An integrated circuit, comprising:

a test mode item signal generating block configured to generate a test mode item signal corresponding to a test mode item;

a coding block configured to code the test mode item signal to generate first and second test control signals; and

first and second internal circuits configured to be test-driven concurrently in response to the corresponding first and second test signals and having no cross-circuit effect.

12. The integrated circuit of claim 11, wherein the test mode item signal generating block is configured to generate a plurality of the test mode item signals that are sequentially activated corresponding to a plurality of the test mode items.

13. The integrated circuit of claim 11, wherein the coding block includes:

a first path configured to pass the test mode item signal to be outputted as the first test control signal; and

a second path configured to invert the test mode item signal to generate the second test control signal.

14. The integrated circuit of claim 11, further comprising:

a test mode entry controlling block configured to generate a test mode entry signal to provide the test mode entry signal to the test mode item signal generating block.

15. The integrated circuit of claim 14, wherein the test mode entry controlling block is configured to generate a pulse signal toggled based on a test address in order to output the pulse signal to the test mode item signal generating block.

16. The integrated circuit of claim 15, wherein the test mode item signal generating block is configured to sequentially latch the test mode entry signal by a predetermined time interval in response to the pulse signal to output a plurality of the test mode item signals.

17. The integrated circuit of claim 16, wherein the test mode item signal generating block includes:

a plurality of shift registers connected in series, the shift registers being configured to output the test mode item signals sequentially,

wherein the shift register of a first stage is configured to latch the test mode entry signal in response to the pulse signal, and the shift registers of the next stage are configured to latch an output of the shift register of the previous stage in response to the pulse signal.

18. The integrated circuit of claim 11, wherein the test mode item signal generating block is configured to be reset by a reset signal.

19. The integrated circuit of claim 11, wherein the test mode item signal generating block and the coding block are disposed adjacent to the first and second internal circuits.

20. The integrated circuit of claim 15, wherein the test mode item signal generating block is configured to receive the test mode entry signal and the pulse signal through a global line.

21. An integrated circuit, comprising:

a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items in response to an input signal applied through a global line;

a coding block configured to receive the plurality of test mode item signals through a first local line and code the plurality of test mode item signals to generate multiple test control signals per each of the test mode item signals; and

a multiplicity of internal circuits configured to receive the multiplicity of test control signals through a second local line, and to be test-driven in response to the corresponding test control signal, wherein at least two internal circuits are configured to be test-driven concurrently.

22. The integrated circuit of claim 21, wherein the test mode item signal generating block is configured to generate the plurality of test mode item signals that are sequentially activated.

23. The integrated circuit of claim 22, wherein the coding block includes a plurality of coding units, each coding unit including:

a first path configured to pass the test mode item signal to be outputted as a first test control signal; and

a second path configured to invert the test mode item signal to generate a second test control signal.

24. The integrated circuit of claim 21, further comprising:

a test mode entry controlling block configured to generate a test mode entry signal as the input signal of the test mode item signal generating block.

25. The integrated circuit of claim 24, wherein the test mode entry controlling block is configured to generate a pulse signal as the input signal, the pulse signal being toggled based on a test address.

26. The integrated circuit of claim 25, wherein the test mode item signal generating block is configured to sequentially latch the test mode entry signal by a predetermined time interval in response to the pulse signal to output the test mode item signals.

27. The test circuit of claim 25, wherein the test mode item signal generating block includes:

a plurality of shift registers connected in series, the shift registers are configured to output the test mode item signals sequentially,

wherein the shift register of a first stage is configured to latch the test mode entry signal in response to the pulse signal, and the shift registers of the next stage are configured to latch an output of the shift register of the previous stage in response to the pulse signal.

28. The test circuit of claim 21, wherein the test mode item signal generating block is configured to be reset by a reset signal.

29. The integrated circuit of claim 21, wherein the test mode item signal generating block and the coding block are disposed adjacent to the internal circuit.

30. The integrated circuit of claim 21, wherein the first local line is provided in at least half the number of the second local lines.

31. A method for testing an internal circuit of an integrated circuit, the method comprising:

generating a test mode item signal corresponding to a test mode item;

coding the test mode item signal to generate at least two test control signals; and

test-driving at least two internal circuit blocks concurrently by using the test control signals.

32. The method of claim 31, further comprising:

generating a plurality of the test mode item signals that are sequentially activated corresponding to a plurality of the test mode items during generating the test mode item signal.

33. The method of claim 32, wherein coding the test mode item signal includes:

passing the test mode item signal to be outputted as a first test control signal; and

inverting the test mode item signal to generate a second test control signal.

34. The method of claim 31, wherein generating the test mode item signal includes:

generating a first test mode item signal by latching a test mode entry signal in response to a pulse signal toggled according to a test address;

delaying the first test mode item signal; and

generating a second test mode item signal by latching the delayed first test mode item signal in response to the pulse signal.