NON-VOLATILE MEMORY STORAGE SYSTEM

• US 20100125695A1
• Filed: 11/15/2008
• Published: 05/20/2010
• Est. Priority Date: 11/15/2008
• Status: Abandoned Application

• Current Assignee: Nanostar Corporation
• Original Assignee: Nanostar Corporation
• Inventors: WU, GARY, Chin, Roger
• Application Number:
  US12/271,885
• Publication Number:
  US 20100125695A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/262 configured as RAID
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present invention discloses a flash memory storage system, comprising at least one RAID controller; a plurality of flash memory cards electrically connected with the RAID controller; and a cache memory electrically connected with the RAID controller and shared by the RAID controller and the flash memory cards. The cache memory efficiently enhances the system performance. The storage system may comprise more RAID controllers to construct a nested RAID architecture.

Claims

1. A flash memory storage system comprising:

a RAID controller;

a plurality of flash memory module electrically connected to the RAID controller; and

a DRAM cache memory shared by the RAID controller and the plurality of flash memory modules.

2. The flash memory storage system of claim 1, wherein the DRAM cache stores FAT and wear-leveling table.

3. The flash memory storage system of claim 1, wherein the DRAM cache is used for data rebuild.

4. The flash memory storage system of claim 1, wherein the RAID controller includes a corresponding plurality of FIFOs.

5. The flash memory storage system of claim 1, wherein the RAID controller includes a DMA engine, and wherein the DRAM cache is used for data pool for DMA transfer under control by the DMA engine.

6. The flash memory storage system of claim 1, wherein the DRAM cache implements double buffering technique with read/write buffers toggling.

7. The flash memory storage system of claim 1, wherein one of the flash memory modules employ down grade flash memory.

8. The flash memory storage system of claim 1, wherein the flash memory modules are one selected from the group consisting of:

solid state drive (SSD), USB flash drive, card bus card, SD flash card, MMC flash card, memory stick, MI card, and Expresscard flash card.

9. The flash memory storage system of claim 1, wherein the memory module communication interface communicates with the flash memory module according to SATA-II, SATA-III, USB 3.0, USB 2.0, PCIe 2.0, PCIe 1.0, SD card T/F, micro SD I/F, or CFast card I/F protocol.

10. The flash memory storage system of claim 1, wherein the RAID controller includes a local SRAM for storing wear-leveling table.

11. A flash memory storage system comprising:

a RAID engine;

a flash controller;

a plurality of flash memory devices electrically connected to the flash controller; and

a DRAM cache memory shared by the RAID engine and the flash controller.

12. The flash memory storage system of claim 11, wherein the DRAM cache stores FAT and wear-leveling table.

13. The flash memory storage system of claim 11, wherein the DRAM cache is used for data rebuild.

14. The flash memory storage system of claim 11, wherein the flash controller includes a plurality of channels, and each channel includes a channel write cache.

15. The flash memory storage system of claim 11, further comprising a DMA engine, wherein the DMA engine performs asynchronous direct memory transfer.

16. The flash memory storage system of claim 15, wherein the channel write cache performs address boundary check.

17. The flash memory storage system of claim 15, wherein the DMA engine does independent channel rewrite or independent re-erase operation.

18. The flash memory storage system of claim 11, wherein one of the flash memory devices employ down grade flash memory.

19. The flash memory storage system of claim 11, wherein the DRAM has a size larger than 1 M Bytes for each channel.

20. The flash memory storage system of claim 11, further comprising a local SRAM electrically connected with the RAID engine for storing wear-leveling table.