Synchronization Controller For Multiple Multi-Threaded Processors

• US 20100125717A1
• Filed: 11/17/2008
• Published: 05/20/2010
• Est. Priority Date: 11/17/2008
• Status: Abandoned Application

• Current Assignee: Mobileye Technologies Limited (Intel Corporation)
• Original Assignee: Mobileye Technologies Limited (Intel Corporation)
• Inventors: Navon, Mois
• Application Number:
  US12/272,290
• Publication Number:
  US 20100125717A1
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A gated-storage system including multiple control interfaces, each control interface operatively connected externally to respective multithreaded processors. The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within any of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.

Claims

1. A gated-storage system comprising:

a plurality of control interfaces, each control interface operatively connected externally to a respective one of a plurality of multi-threaded processors each having at least one thread context running at least one active thread so that a plurality of said thread contexts are running on said multithreaded processors;

a memory operatively connected to a system-level inter-thread communications unit and shared between the multithreaded processors, wherein said thread contexts request access to said memory by communicating a plurality of access requests over said control interfaces, said access requests originating from any of said thread contexts within any of said multithreaded processors;

a single request storage shared by the multithreaded processors; and

a controller adapted to store said access requests in said request storage.

2. The system, according to claim 1, wherein said access requests are from at least two of said thread contexts and from at least two of said multithreaded processors.

3. The system, according to claim 1, wherein said multithreaded processors are of at least two different architectures.

4. The system, according to claim 1, wherein said system-level inter-thread communications unit is a single inter-thread communications unit in the gated storage system.

5. The system, according to claim 1, wherein said controller and said request storage are adapted to store, in said request storage, during a single clock cycle, one of said access requests from any of said multithreaded processors.

6. The system, according to claim 1, wherein said controller and said request storage are adapted to store, in said request storage, during a single clock cycle, at least two of said access requests from least two said multithreaded processors.

7. The system, according to claim 6, wherein, during said single clock cycle, said controller and said request storage are further adapted to deallocate one of said access requests, thereby removing said one access request from said request storage, while simultaneously accepting others of said access requests from said multithreaded processors.

8. The system, according to claim 1, wherein said controller is adapted to handle a kill request and thereby removing from said request storage any of said access requests from any of said multithreaded processors by receiving, via said plurality of control interfaces, at least one identifier identifying at least one of said thread contexts.

9. The system, according to claim 1, wherein said controller is adapted for handling said access requests from any of said multithreaded processors by receiving via said control interfaces at least one identifier identifying at least one of said thread contexts.

10. In a gated-storage system including a plurality of control interfaces operatively attached externally to a respective one of a plurality of multithreaded processors and a gated memory operatively connected to a system-level inter-thread communications unit and shared between the multithreaded processors, a method for synchronization of data comprising:

running at least one active thread in each of the multithreaded processors by a plurality of thread contexts on the multithreaded processors;

requesting access to the gated memory by communicating a plurality of access requests over said control interfaces, said access requests originating from any said thread contexts within any of the multithreaded processors;

sharing a single request storage by the multithreaded processors; and

storing all access requests from the multithreaded processors in said single request storage.

11. The method according to claim 10, further comprising storing, in said request storage, during a single clock cycle, one of said access requests from any of the multithreaded processors.

12. The method according to claim 10, further comprising storing, in said request storage, during a single clock cycle, at least two access requests from at least two of the multithreaded processors.

13. The method according to claim 12, further comprising deallocating one of said access requests, thereby removing said one access request from said request storage during said single clock cycle.

14. The method according to claim 10, further comprising handling access requests from any of the multithreaded processors by receiving, via said control interfaces, at least one identifier identifying any of said thread contexts.

15. The method according to claim 10, further comprising handling a kill request and thereby removing from said request storage any access requests from any of the multithreaded processors by receiving via said control interfaces at least one identifier identifying at least one of said thread contexts.

16. A system comprising:

a plurality of multi-threaded processors, each multi-threaded processor configured to have at least one thread context running at least one active thread;

a system-level inter-thread communications unit that includes a plurality of control interfaces, each control interface operatively connecting to a respective one of the plurality of multi-threaded processors,

a gated memory operatively connecting to the system-level inter-thread communications unit, and shared by the multithreaded processors, wherein the thread contexts request access to said gated memory by communicating a plurality of access requests over said control interfaces, said access requests originating from any of said thread contexts within any of said multithreaded processors;

a single request storage operatively connected to the control interfaces; and

a controller adapted to store said access requests in said single request storage.