INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS

• US 20100127309A1
• Filed: 11/21/2008
• Published: 05/27/2010
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Baier, Steven, de Jong, Jan Lodewijk
• Granted Patent: US 7,944,732 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed in a second metal layer of the IC extending along the axis and connected to the first node plate with a via. A third node plate link formed in the first metal layer is electrically connected to and forming a portion of a second node of the capacitor and extends along a second axis (x) of the node plate array transverse to the first node plate link, proximate to an end of the first node plate link and overlying a portion of the second node plate link.

Claims

1. A capacitor in an integrated circuit (“

IC”

) comprising;

a first node plate link formed in a first metal layer of the IC electrically connected to and forming a first portion of a first node of the capacitor having a length and a width, the length extending along a first axis of a node plate array of the capacitor;

a second node plate link formed in a second metal layer of the IC;

a first via electrically connecting the first node plate link and the second node plate link, the second node plate link extending along the first axis from the first via; and

a third node plate link formed in the first metal layer electrically connected to and forming a first portion of a second node of the capacitor, the third node plate extending along a second axis of the node plate array transverse and proximate to an end of the first node plate link and overlying a portion of the second node plate link.

2. The capacitor of claim 1 wherein the third node plate link has the length and the width.

3. The capacitor of claim 1 wherein the portion of the second node plate link overlain by the third node plate link is a square portion.

4. The capacitor of claim 1 further comprising

a fourth node plate link having the length and the width formed in the first metal layer of the IC;

and

a second via electrically connecting the fourth node plate link and the second node plate link, the fourth node plate link extending along the first axis from the second via.

5. The capacitor of claim 1 further comprising a second via electrically connecting the first node plate link to the second node plate link at an end of the first node plate link.

6. The capacitor of claim 5 wherein the length is 6f and the width is 3f, f being a minimum critical dimension of the first metal layer.

7. The capacitor of claim 1 wherein an aspect ratio of the length to the width is not greater than 5:

1.

8. The capacitor of claim 1 further comprising

a first bus bar extending along a first edge of the node plate array electrically connected to and forming a second portion of the first node of the capacitor;

a second bus bar extending along a second edge of the node plate array opposite the first edge and electrically connected to and forming a third portion of the first node of the capacitor;

a first series of node plate links including the first node plate link and the second node plate link alternating between the first metal layer and the second metal layer extending between the first buss and the second bus bar;

a third bus bar extending along a third edge of the node plate array orthogonal to the first bus bar electrically connected to and forming a second portion of the second node of the capacitor;

a fourth bus bar extending along a fourth edge of the node plate array opposite the third edge and electrically connected to and forming a third portion of the second node of the capacitor; and

a second series of node plate links including the third node plate link alternating between the first metal layer and the second metal layer extending between the third bus bar and the fourth bus bar.

9. The capacitor of claim 8 wherein the first series of node plate links includes a first plurality of H-elements and the second series of node plate links includes a second plurality of H-elements, each of the first plurality of H-elements overlying corresponding H-elements of the second plurality of H-elements, each of the first plurality of H-elements being rotated ninety degrees relative to the corresponding H-elements.

10. The capacitor of claim 8 further comprising a second node plate array having a third series of node plate links electrically connected to one of the first bus bar, the second bus bar, the third bus bar and the fourth bus bar extending away from the first node plate array.

11. The capacitor of claim 1 wherein the first node of the capacitor is electrically equivalent to the second node of the capacitor.

12. The capacitor of claim 11 wherein the IC is a field-programmable gate array (“

FPGA”

) and the capacitor is in a transceiver section of the FPGA.

13. The capacitor of claim 1 further comprising a second via electrically connecting the first node plate link to the second node plate link, the second via being adjacent to the first via along the width of the first node plate link at a first end of the first node plate link.

14. The capacitor of claim 1 wherein the capacitor is located in an analog-to-digital converter.

15. The capacitor of claim 1 wherein the integrated circuit is a field programmable gate array.