3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES

• US 20100127345A1
• Filed: 11/25/2008
• Published: 05/27/2010
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Jones, Robert E., Petras, Michael F., Ramiah, Chandrasekaram, Sanders, Paul W.
• Granted Patent: US 8,344,503 B2
• Time in Patent Office: Days
• US Class Current: 257/528
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83365 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/58 : Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.

Claims

1. A 3-D integrated circuit (IC), comprising:

an active device (AD) substrate having an AD region thereon with device contacts therein;

an isolator substrate, separately formed from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate; and

an integrated passive device (IPD) substrate, separately formed from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having one or more TSVs there through, adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate.

2. The integrated circuit of claim 1, wherein at least some of the TSVs in the isolator substrate are coupled to some of the device contacts in the AD region on the AD substrate.

3. The integrated circuit of claim 1, further comprising a further interconnect zone located between the second isolator substrate and the third IPD substrate.

4. The integrated circuit of claim 3, wherein some of the device contacts on the AD substrate are coupled to other device contacts on the AD substrate via the further interconnect zone.

5. The integrated circuit of claim 3, wherein some of the IPDs are coupled to other of the IPDs via the further interconnect zone.

6. The integrated circuit of claim 3, wherein at least one of the IPDs has a first element located in the IPD zone and a second element located in the further interconnect zone.

9. The integrated circuit of claim 1, wherein the isolator substrate has a resistivity of a 1000 ohm-cm or greater.

10. The integrated circuit of claim 1, wherein the isolator substrate has a thickness in the range of about 10 and 200 micrometers or larger.

11. The integrated circuit of claim 1, wherein the IPD substrate has a resistivity of a 1000 ohm-cm or greater.

12. The integrated circuit of claim 1, wherein the isolator substrate has a thickness in the range of about 10 and 200 micrometers or larger.

13. The integrated circuit of claim 1, wherein the AD substrate has a first thickness, the isolator substrate has a second thickness and the IPD substrate has a third thickness, and at least one or both of the second and third thickness are at least about 2-20 times the first thickness.

14. A method for forming a 3-D integrated circuit (IC), comprising:

forming on separate substrates at least an active device chip, an isolator chip and an integrated passive device (IPD) chip, wherein at least two of such chips have one or more conductor filled vias extending there through and wherein at least some vias in the IPD chip are coupled to one or more integrated components on the IPD chip;

stacking the active device chip, the isolator chip and the IPD chip so that a first via in a first of the at least two chips is aligned with a second via in another of the at least two chips; and

bonding the active device chip, the isolator chip and the integrated passive device (IPD) chip together so that the first and second vias are electrically coupled.

15. The method of claim 14, wherein the forming step comprises, forming the active device chip, the isolator chip and the IPD chip with one or more levels of interconnects on first surfaces thereof, some of which are coupled during the bonding step with one or more vias exposed on a rear face of a chip to which it is being bonded in the bonding step.

16. The method of claim 14, wherein the forming step comprises:

providing an initial substrate having a front face and a rear face;

etching a blind via cavity in the initial substrate extending from the front face toward the rear face;

filling the blind cavity with a conductor having an interior surface proximate a bottom of the cavity;

removing excess conductor from above the blind cavity to expose a first face of the conductor filling the blind cavity;

mounting the substrate on a support with the first face toward the support;

removing material from the rear face of the initial substrate thereby providing a thinned substrate having therein a conductor filled via of depth d extending there through and with the first face and the interior surface of the conductor in the cavity exposed; and

removing the support from the thinned substrate.

17. The method of claim 16, further comprising:

providing an interconnect zone on the front face of the initial substrate; and

wherein the step of removing excess conductor comprises removing excess conductor over the interconnect zone.

18. A 3-D integrated circuit (IC), comprising:

an active device chip formed on an active device substrate having an active device interconnect zone on a first face thereof and one or more first conductor filled vias extending from the first face to an opposite second face thereof;

an isolator chip formed on an isolator substrate having a further interconnect zone on a first face thereof coupled to one or more second conductor filled vias extending from the first face to an opposite second face thereof;

a third chip containing integrated passive devices or other elements or both formed on a third substrate and having an interconnect zone on a first face thereof coupled to one or more third conductor filled vias extending from the first face to an opposite second face thereof, and

wherein the active device chip, the isolator chip and third chip are bonded together so that at least some of the third conductor filled vias are coupled to at least some of the second conductor filled vias.

19. The 3-D IC of claim 18, wherein at least some of the second conductor filled vias are coupled to one or more of the first conductor filled vias.

20. The 3-D IC of claim 19, wherein the active device interconnect zone on the active device chip couples at least one of the active devices on the active device chip to one or more of the first conductor filled vias.