INTEGRATED CAPICITOR WITH CABLED PLATES

• US 20100127348A1
• Filed: 11/21/2008
• Published: 05/27/2010
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Quinn, Patrick J.
• Granted Patent: US 8,362,589 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A capacitor in an integrated circuit (“IC”) has a distribution grid formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament connected to and extending away from the distribution grid along a first direction. A second vertical conductive filament is connected to the distribution grid and extends in the opposite direction. First and second grid plates are formed in the metal layers above and below the first patterned metal layer. The grid plates surround the first and second vertical conductive filaments. The distribution grid, first vertical conductive filament and second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a portion of a second node of the capacitor.

Claims

1. A capacitor in an integrated circuit (“

IC”

) comprising;

a distribution grid formed in a first patterned metal layer of the integrated circuit;

a first vertical conductive filament connected to and extending away from the distribution grid along a first direction;

a second vertical conductive filament connected to and extending away from the distribution grid along a second direction opposite the first direction;

a first grid plate formed in a second patterned metal layer proximate to the first patterned metal layer, the first grid plate surrounding the first vertical conductive filament in the second patterned metal layer;

a second grid plate formed in a third patterned metal layer proximate to the first patterned metal layer, the first patterned metal layer disposed between the second patterned metal layer and the third patterned metal layer, the second grid plate surrounding the second vertical conductive filament in the third patterned metal layer, wherein the distribution grid, the first vertical conductive filament and the second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a first portion of a second node of the capacitor.

2. The capacitor of claim 1 wherein the first node is a top node of a switching capacitor in the IC.

3. The capacitor of claim 1 wherein the first patterned metal layer further includes a perimeter shield conductor connected to and forming a second portion of the second node at least partially surrounding the distribution grid in the first patterned metal layer.

4. The capacitor of claim 3 wherein the first patterned metal layer further includes a center tap extending through a gap in the perimeter shield conductor to the distribution grid.

5. The capacitor of claim 1 further comprising:

a first number of grid plates above the first patterned metal layer, and a second number of grid plates below the first patterned metal layer, the first vertical conductive filament being surrounded by each of the first number of grid plates, and the second vertical conductive filament being surrounded by each of the second number of grid plates.

6. The capacitor of claim 5 wherein the first number equals the second number.

7. The capacitor of claim 5 wherein one of the second number of grid plates is formed in a polysilicon or silicide layer of the IC.

8. The capacitor of claim 1 wherein the first grid plate is connected to the second grid plate through the distribution grid.

9. The capacitor of claim 1 comprising a first plurality of vertical conductive filaments extending through and being surrounded by the first grid plate and a second plurality of vertical conductive filaments extending through and being surrounded by the second grid plate.

10. The capacitor of claim 9 further comprising a first plate encasing covering first ends of the first plurality of vertical conductive filaments, the first plate encasing being connected to the second node.

11. The capacitor of claim 10 further comprising a second plate encasing covering second ends of the second plurality of vertical conductive filaments, the second plate encasing being connected to and forming a third portion of the second node.

12. The capacitor of claim 11 wherein the second plate encasing is formed in a polysilicon or silicide layer of the IC.

13. The capacitor of claim 1 wherein the capacitor is located in an analog-to-digital converter.

14. The capacitor of claim 1 wherein the capacitor is located in a transceiver.

15. The capacitor of claim 1 wherein the integrated circuit is a field programmable gate array.