INTEGRATED CAPACITOR WITH INTERLINKED LATERAL FINS

• US 20100127351A1
• Filed: 11/21/2008
• Published: 05/27/2010
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Quinn, Patrick J.
• Granted Patent: US 7,956,438 B2
• Time in Patent Office: Days
• US Class Current: 257/534
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A capacitor in an integrated circuit (“IC”) has a first node conductor formed in a first metal layer of the IC with a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to the first direction. A first capital element extends along the first direction, and a first serif element extends from the capital element. The capacitor also has a second node conductor having a second spine, a second vertical element extending from the second spine toward the first spine, a second capital element, and a second serif element extending from the second capital between the first vertical element and the first serif element.

Claims

1. A capacitor in an integrated circuit (“

IC”

) comprising;

a first node conductor formed in a first metal layer of the IC having a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to the first direction, a first capital element extending along the first direction, and a first serif element extending from the first capital element toward the first spine; and

a second node conductor formed in the first metal layer of the IC having a second spine extending along the first direction, a second vertical element extending from the second spine along the second direction toward the first spine, a second capital element extending along the first direction between the first spine and the second spine, and a second serif element extending from the second capital element toward the second spine, the second serif element being disposed between the first vertical element and the first serif element.

2. The capacitor of claim 1 further comprising a third serif element extending from the first capital element toward the first spine, the first capital element extending between the first serif element and the third serif element so as to form a first fin on the first spine.

3. The capacitor of claim 2 further comprising a third vertical element extending from the second spine to a third capital element, a fourth serif element extending from the third capital element toward the second spine between the first vertical element and the third serif element.

4. The capacitor of claim 2 further comprising a second fin having a third vertical element extending in the second direction from the second spine opposite the first vertical element.

5. The capacitor of claim 4 wherein the first fin is a first T-shaped fin and the second fin is a second T-shaped fin interlinking with the first T-shaped fin.

6. The capacitor of claim 2 further comprising a first plurality of fins extending from the first spine toward the second spine and a second plurality of fins extending from the second spine interlinked with the first plurality of fins.

7. The capacitor of claim 6 further comprising a third plurality of fins extending from the first spine away from the second spine.

8. The capacitor of claim 7 wherein each of the third plurality of fins is opposite a corresponding each of the first plurality of fins along the first spine.

9. The capacitor of claim 6 wherein the second node conductor is a top node conductor and the second spine is an outermost spine of the top node conductor, the first node conductor further comprising a first node shield bar extending along the outermost spine of the top node conductor.

10. The capacitor of claim 6 wherein the second node conductor is a top node conductor further comprising a buss bar extending along the second direction, the second spine extending from the buss bar, and the first node conductor further comprising a first node shield bar extending along the buss bar.

11. The capacitor of claim 6 wherein the second node conductor is a top node conductor further comprising a buss bar and the second spine is an outermost spine of the top node conductor extending from the buss bar, the first node conductor further comprising a first node shield bar extending along the buss bar and a second node shield bar extending along the outermost spine.

12. The capacitor of claim 6 further comprising a second metal layer of the IC having a third plurality of fins overlying the first plurality of fins, and a fourth plurality of fins overlying the second plurality of fins.

13. The capacitor of claim 12 wherein the third plurality of fins is electrically connected to the first plurality of fins with a first plurality of conductive vias, and the fourth plurality of fins is electrically connected to the second plurality of fins with a second plurality of conductive vias.

14. A capacitor in an integrated circuit (“

IC”

) comprising;

a first node conductor formed in a metal layer of the IC having a first node buss bar, a plurality of first node spines extending from the first node buss bar, a first plurality of T-shaped fins extending from a first node spine in a first direction and a second plurality of T-shaped fins extending from the first node spine in a second direction opposite the first direction; and

a second node conductor formed in the metal layer having a second node buss bar, a plurality of second node spines extending from the second node buss bar, a third plurality of T-shaped fins extending from a second node spine in the first direction and interlinking with at least some of the second plurality of T-shaped fins.

15. The capacitor of claim 14 wherein the first node is a bottom node of a switching capacitor and the first node conductor further includes bottom node shield bar proximate to and extending along the second node buss bar.

16. The capacitor of claim 15 wherein the first node conductor further includes a second bottom node shield bar proximate to and extending along the second node spine.

17. The capacitor of claim 14 wherein the second plurality of T-shaped fins is a mirror image of the first plurality of T-shaped fins.

18. The capacitor of claim 14 further comprising

a second plurality of first node spines in a second metal layer of the IC and a fourth plurality of T-shaped fins connected to the first node in the second metal layer overlying the first plurality of T-shaped fins in the first metal layer;

a second plurality of second node spines in the second metal layer of the IC and a fifth plurality of T-shaped fins connected to the second node in the second metal layer overlying the third plurality of T-shaped fins;

a first plurality of conductive vias connecting at least some of the T-shaped fins in the first plurality to at least some of the T-shaped fins in the fourth plurality; and

a second plurality of conductive vias connecting at least some of the T-shaped fins in the third plurality to at least some of the T-shaped fins in the fifth plurality.

19. The capacitor of claim 14 further comprising

a second plurality of first node spines in a second metal layer of the IC and a fourth plurality of T-shaped fins connected to the first node in the second metal layer overlying the third plurality of T-shaped fins connected to the second node in the first metal layer;

and

a second plurality of second node spines in the second metal layer of the IC and a fifth plurality of T-shaped fins connected to the second node in the second metal layer overlying the first plurality of T-shaped fins connected to the first node in the first metal layer.

20. The capacitor of claim 14 wherein the IC is a field-programmable gate array having an analog section and further comprising a reference shield plate formed in an analog ground layer of the analog section.