THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS

• US 20100127394A1
• Filed: 11/25/2008
• Published: 05/27/2010
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Petras, Michael F., Ramiah, Chandrasekaram, Sanders, Paul W., Mitchell, Douglas G.
• Granted Patent: US 7,935,571 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18′); etching (104) via cavities (29) partly through the wafer (18′) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18′) with its front side (35) facing a support structure (40); thinning (107) the wafer (18′) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.) of the filled vias; removing (109) the support structure (40) and separating the individual device or IC assemblies (48) so as to be available for mounting (110) on a further circuit board, tape or larger circuit (50).

Claims

1. A method for forming through-substrate conductor filled vias for back-side electrical or thermal interconnections or both on a thinned substrate, comprising:

providing desired device regions with contacts on a front surface of an initial substrate having a back side;

forming via cavities to depth d′

from the front surface partly through the initial substrate in desired locations;

filling the via cavities with a conductive material coupled to some device region contacts;

mounting the initial substrate with its front surface coupled to a support structure;

thinning the initial substrate from the back side to provide a final substrate that is thinner than the initial substrate and on whose back surface are exposed internal ends of the conductive material filled vias;

applying any desired back-side interconnect region coupled to the one or more exposed ends of the conductive material filled vias; and

removing the support structure and separating individual device or IC assemblies of the final substrate so as to be available for mounting on a further circuit board, tape or larger circuit.

2. The method of claim 1, further comprising, prior to the filling step, providing one or more refractory liners in the via cavities.

3. The method of claim 2, wherein the one or more refractory liners comprise a dielectric liner.

4. The method of claim 2, wherein the one or more refractory liners comprise a barrier layer for inhibiting diffusion of the conductive material into the final substrate.

5. The method of claim 2, wherein the one or more refractory liners comprise an adhesion layer for attachment of the conductive material to the final substrate in the via cavities.

6. The method of claim 2, wherein the via cavities have a width w and the one or more refractory liners have a thickness less than about 20% of w.

7. The method of claim 1, wherein the final substrate has a thickness of about 20 micrometers or less and the back-side interconnect region has a thickness of at least about 30% to 50% of the final substrate thickness.

8. The method of claim 1, wherein the initial substrate has a first thickness and the final substrate has a second thickness and the second thickness is less than or equal about 20% of the first thickness.

9. The method of claim 8, wherein the initial substrate has a first thickness and the final substrate has a second thickness and the second thickness is less than or equal about 10% of the first thickness.

10. The method of claim 9, wherein the initial substrate has a first thickness and the final substrate has a second thickness and the second thickness is less than or equal about 5% of the first thickness.

11. An electronic assembly formed by a process, comprising:

providing an initial substrate having an active device region proximate a first surface thereof;

forming via cavities extending part-way through the initial substrate from the first surface;

filling the via cavities with a conductive material at least partly coupled to some part of the active device region;

mounting the initial substrate on a temporary support structure with the first surface facing the temporary support structure and a rear face of the initial substrate exposed;

removing material from the rear face until a new surface is reached of a thinned substrate on which interior ends of the via cavities filled with the conductive material are exposed;

providing a further interconnect region on the new surface making contact to at least some of the interior ends of the via cavities filled with the conductive material; and

removing the temporary support structure.

12. The device of claim 11, wherein the thinned substrate has a thickness less than or equal to about 20% of a thickness of the initial substrate.

13. The device of claim 11, wherein the via cavities have a refractory liner.

14. The device of claim 13, wherein the refractory liner comprises one or more of an insulating material, a barrier material, or an adhesion material.

15. The device of claim 11, wherein the further interconnect region has a thickness of 30% to 50% of the thickness of the thinned substrate.

16. A method for forming electronic assemblies, comprising:

providing an initial semiconductor substrate of a first thickness and having a region of active devices proximate a first surface thereof;

forming via cavities extending part-way through the initial semiconductor substrate from the first surface;

filling the via cavities with a conductive metal coupled to some of the active devices;

mounting the initial semiconductor substrate on a temporary support structure with the first surface facing the temporary support structure and a rear face of the initial semiconductor substrate exposed;

removing material from the rear face until a new surface is reached on which interior ends of the metal filled via cavities are exposed, thereby forming a thinned semiconductor substrate of a second thickness and still having the region of active devices proximate the first surface;

providing a further interconnect region on the new surface making contact to some or all of the interior ends of the via cavities filled with the conductive metal; and

removing the temporary support structure.

17. The method of claim 16, further comprising, during or after the providing the initial semiconductor substrate step, forming one or more interconnect levels on the first surface coupling some of the active devices to each other or to locations that can be contacted by part of the conductive metal during the filling step or both.

18. The method of claim 16, wherein the removing material step removes at least 80% of the first thickness.

19. The method of claim 16, wherein the further interconnect region has a third thickness at least equal to 30% to 50% of the second thickness.

20. The method of claim 16, wherein the removing material step comprises chemical-mechanical-polishing.