Internal charge transfer for circuits

• US 20100127730A1
• Filed: 11/21/2008
• Published: 05/27/2010
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cho, Choongyeun, Kim, Moon J., Kim, Daeik, Corbin, Elmer K.
• Granted Patent: US 7,804,329 B2
• Time in Patent Office: Days
• US Class Current: 326/34
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture.

Claims

1. A circuit comprising:

a supply voltage node;

a ground voltage node;

a set of backgate voltage nodes; and

a charge transfer mechanism coupled to the supply voltage node, the ground voltage node, and the set of backgate voltage nodes, the charge transfer mechanism being configured to transfer charge among the supply voltage node, the ground voltage node, and the set of backgate voltage nodes.

2. The circuit of claim 1, the charge transfer mechanism being configured to transfer charge from the supply voltage node to the ground voltage node to put the circuit into a sleep mode.

3. The circuit of claim 1, the charge transfer mechanism being configured to transfer charge from the set of backgate voltage nodes to the ground voltage node and the supply voltage node to bring the circuit out of a sleep mode.

4. The circuit of claim 1, further comprising a logic system communicating with the set of backgate voltage nodes, the supply voltage node, and the ground voltage node.

5. The circuit of claim 1, the charge transfer mechanism comprising a set of switches, the set of switches coupling together the set of backgate voltage nodes, the supply voltage node, and the ground voltage node when closed.

6. The circuit of claim 1, the set of backgate voltage nodes comprising a PFET backgate voltage node and a NFET backgate voltage node.

7. The circuit of claim 6, the set of switches comprising:

a first switch positioned between the supply voltage node and the ground voltage node;

a second switch positioned between the PFET backgate voltage node and the supply voltage node; and

a third switch positioned between the NFET backgate voltage node and the ground voltage node.

8. A digital circuit comprising:

a supply voltage node;

a ground voltage node;

a PFET backgate voltage node;

a NFET backgate voltage node; and

a set of switches coupled to the set of backgate voltage nodes, the supply voltage node, and the ground voltage node, the set of switches being configured to transfer charge;

between the supply voltage node and the ground voltage node,

between the PFET backgate voltage node and the supply voltage node, and

between the NFET backgate voltage node and the ground voltage node.

9. The digital circuit of claim 8, the set of switches transferring the charge to bring the digital circuit in and out of a sleep mode.

10. The digital circuit of claim 8, further comprising a digital logic system coupling together the set of backgate voltage nodes, the supply voltage node, and the ground voltage node.

11. The digital circuit of claim 8, a set of switches comprising:

a first switch positioned between the supply voltage node and the ground voltage node;

a second switch positioned between the PFET backgate voltage node and the supply voltage node; and

a third switch positioned between the NFET backgate voltage node and the ground voltage node.

12. A method for transferring charge in a circuit, comprising:

transferring a supply voltage charge from a supply voltage node to a ground voltage node to put the circuit into a sleep mode; and

transferring a backgate voltage charge from a set of backgate voltage nodes to the supply voltage node and the ground voltage node to bring the circuit out of the sleep mode.

13. The method of claim 12, further comprising a logic system communicating with the set of backgate voltage nodes, the supply voltage node, and the ground voltage node.

14. The method of claim 12, the transferring of the supply voltage charge and the backgate voltage charge being enabled via a set of switches in the circuit, the set of switches coupling together the set of backgate voltage nodes, the supply voltage node, and the ground voltage node.

15. The method of claim 14, the set of backgate voltage nodes comprising a PFET backgate voltage node and an NFET backgate voltage node.

16. The method of claim 15, the set of switches comprising:

a first switch positioned between the supply voltage node and the ground voltage node;

a second switch positioned between the PFET backgate voltage node and the supply voltage node; and

a third switch positioned between the NFET backgate voltage node and the ground voltage node.

17. The method of claim 16, the transferring of the supply voltage charge comprising closing the first switch.

18. The method of claim 16, the transferring of the backgate voltage charge comprising closing the second switch and the third switch.

19. A method for changing modes of a digital circuit, comprising:

closing a first switch in the digital circuit;

transferring a supply voltage charge from a supply voltage node to a ground voltage node using the first switch to put the digital circuit into a sleep mode;

opening the first switch;

closing a second switch and a third switch in the digital circuit; and

transferring a backgate voltage charge from a set of backgate voltage nodes to the supply voltage node and the ground voltage node using the second switch and the third switch to bring the digital circuit out of the sleep mode.

20. The method of claim 19:

the first switch being positioned between the supply voltage node and the ground voltage node;

the second switch being positioned between a PFET backgate voltage node and the supply voltage node; and

a third switch being positioned between a NFET backgate voltage node and the ground voltage node.