Variable PFC and grid-tied bus voltage control
First Claim
1. A device for generating a compensation signal for a power converter comprising:
- a) a frequency-locked clock, coupled to an AC-line having an AC-line voltage frequency, generating a frequency that is frequency locked to an integral multiple of the AC-line voltage frequency;
b) a bus-voltage sampler, operatively coupled to the frequency-locked clock and coupled to a power converter bus having a bus-voltage, generating bus-voltage data at the frequency;
c) a stack of the bus-voltage data, operatively coupled to the bus-voltage sampler, wherein the stack is structured to contain bus-voltage data sampled from a time interval of one-half cycle of the AC-line voltage; and
d) a compensation module, operatively coupled to the stack and configured to generate from the bus-voltage data a compensation signal, and wherein the compensation module is configured to produce a compensation signal in which the frequency components at even multiples of AC-line voltage frequency are minimized.
1 Assignment
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Accused Products
Abstract
An apparatus for generating a compensation signal for a power converter where the second harmonic ripple on the voltage bus is substantially removed from the compensation signal. The apparatus comprises a frequency-locked clock generator, a bus voltage data generator, a stack, and a compensation signal generator. The frequency-locked clock is coupled to the power converter voltage bus that contains harmonics of the AC line frequency. The clock generator frequency locks to the second harmonic of the AC line frequency and creates a system clock which is used for the synchronous operations throughout the apparatus. The bus-voltage data generator inputs a power converter scaled-bus voltage, generates bus-voltage data at a sampling rate which is determined by the coupled system clock. The output of the bus-voltage generator is input into a stack. The output of the stack is coupled to a summer to remove the second harmonic ripple, and is used by a modified PID′ filter to generate a compensation signal for a power converter controller.
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Citations
35 Claims
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1. A device for generating a compensation signal for a power converter comprising:
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a) a frequency-locked clock, coupled to an AC-line having an AC-line voltage frequency, generating a frequency that is frequency locked to an integral multiple of the AC-line voltage frequency; b) a bus-voltage sampler, operatively coupled to the frequency-locked clock and coupled to a power converter bus having a bus-voltage, generating bus-voltage data at the frequency; c) a stack of the bus-voltage data, operatively coupled to the bus-voltage sampler, wherein the stack is structured to contain bus-voltage data sampled from a time interval of one-half cycle of the AC-line voltage; and d) a compensation module, operatively coupled to the stack and configured to generate from the bus-voltage data a compensation signal, and wherein the compensation module is configured to produce a compensation signal in which the frequency components at even multiples of AC-line voltage frequency are minimized. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of generating a compensation signal for a power converter comprising the steps:
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a) generating a frequency-locked clock having a frequency that is locked to an integral multiple of an AC-line voltage frequency; b) generating bus-voltage data at the frequency, from a power converter bus-voltage; c) queuing the bus-voltage data, wherein a stack is structured to contain bus-voltage data spanning a time interval of one-half cycle of the AC-line voltage; and d) compensating the bus-voltage data and forming a compensation signal, wherein the compensating minimizes the frequency components in the compensation signal that are at even multiples of the AC-line voltage frequency. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method of manufacturing a device for generating a compensation signal for a power converter, comprising the steps:
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a) providing a frequency-locked clock coupled to an AC-line having an AC-line voltage frequency, wherein the clock is configured to generate a frequency that is frequency locked to an integral multiple of the AC-line voltage frequency; b) providing a bus-voltage sampler coupled to the frequency-locked clock and coupled to a power converter bus having a bus-voltage and generating bus-voltage data at the frequency; c) providing a stack coupled to the bus-voltage sampler, wherein the stack is structured to contain bus data-samples spanning a time interval of one-half cycle of the AC-line voltage; and d) providing a compensation module, operatively coupled to the stack, and configured to generate from the bus-voltage data a compensation signal, and wherein the compensation signal module is configured to produce a compensation signal in which the frequency components at even multiples of AC-line voltage frequency are minimized. - View Dependent Claims (31, 32, 33, 34, 35)
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Specification