LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME

• US 20100128192A1
• Filed: 08/25/2009
• Published: 05/27/2010
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: PARK, Jeong-Eun, KIM, Hee-Joon
• Granted Patent: US 8,218,117 B2
• Time in Patent Office: Days
• US Class Current: 349/46
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/134381 Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

An LCD is manufactured to provide a wide viewing angle device and may reduce manufacturing costs according to an embodiment. The LCD includes a substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line contacting the semiconductor layer, a drain electrode contacting the semiconductor layer and separated from the data line, a pixel electrode contacting the drain electrode, a passivation layer disposed on the pixel electrode, and a common electrode disposed on the passivation layer and including a branch electrode overlapping the pixel electrode. In one embodiment, the pixel electrode contacts an end portion of a thin film transistor. The LCD manufacturing process may be shortened and may save manufacturing costs because the LCD process need not make contact holes to connect the pixel electrode and the TFT.

Claims

1. A liquid crystal display (LCD) comprising:

a substrate;

a gate line disposed on the substrate and extending in a first direction;

a data line extending in a second direction intersecting the first direction;

a thin film transistor including a channel region formed in a central portion of the thin film transistor and a drain electrode;

a first passivation layer disposed on the data line;

a pixel electrode disposed on the first passivation layer and contacting the drain electrode;

a second passivation layer disposed on the pixel electrode; and

a common electrode disposed on the second passivation layer, wherein the common electrode includes a branch electrode overlapping the pixel electrode.

2. The LCD of claim 1, wherein the thin film transistor includes:

a gate electrode divided from the gate line;

a gate insulating layer disposed on the gate electrode;

a semiconductor pattern disposed on the gate insulating layer and overlapping the gate electrode;

a source electrode divided from the data line; and

wherein

the drain electrode is disposed on the semiconductor pattern facing the source electrode.

3. The LCD of claim 2, wherein the drain electrode is overlapped by the pixel electrode entirely.

4. The LCD of claim 1, wherein one of either the pixel electrode or the common electrode includes a planar shape, and the other one of either the pixel electrode or the common electrode includes a plurality of linear electrodes and at least one connection portion connecting the plurality of linear electrodes.

5. The LCD of claim 4, wherein the plurality of linear electrodes is slanted to the gate line.

6. The LCD of claim 5, wherein the plurality of linear electrodes is disposed symmetrically about a center line parallel to the gate line.

7. The LCD of claim 1, wherein the common electrode shields the data line.

8. The LCD of claim 1, wherein the common electrode is connected to a neighboring common electrode of a neighboring pixel through a connection portion.

9. The LCD of claim 1, wherein the common electrode includes a substantially planar shape with a plurality of openings.

10. The LCD of claim 1, further comprising;

a storage line formed in a same layer with the gate line or the data line and electrically connected to the common electrode.

11. A method of manufacturing a liquid crystal display (LCD), the method comprising:

forming a gate line and a gate electrode on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor pattern including a channel region and located on the gate insulating layer;

forming a data line, a source electrode, and a drain electrode on the gate insulating layer;

forming a first passivation layer on the data line;

forming a pixel electrode contacting the drain electrode, and contacting the first passivation layer;

forming a second passivation layer on the pixel electrode; and

forming a common electrode on the second passivation layer.

12. The method claim 11, wherein the forming of the first passivation layer comprises using a slit mask or a halftone mask to pattern the first passivation layer.

13. The method of claim 12, wherein the forming of the first passivation layer on the data line further comprises:

forming a photo resist pattern including a first region having a first thickness on the pixel electrode, a second region having a second thickness on the gate electrode, and an opening region on an end portion of the gate line or the data line exposing the first passivation layer, wherein the first thickness is larger than the second thickness; and

etching the first passivation layer using the photo resist pattern as an etching mask to expose an end portion of the gate line or data line in the opening region.

14. The method of claim 13, wherein the forming of the source electrode and the drain electrode comprises;

etching the photo resist pattern of the second region to expose the first passivation layer located on the channel region of the semiconductor pattern; and

etching the first passivation layer above the channel region.

15. The method of claim 11, wherein the forming of the pixel electrode further comprises;

forming a pixel electrode by depositing a pixel electrode layer; and

etching the pixel electrode layer and a data metal layer on the channel region.

16. The method of claim 15, wherein the source electrode and the drain electrode are formed after depositing the pixel electrode layer and patterning the pixel electrode layer and the data metal layer on the channel region.

17. The method of claim 16, wherein the drain electrode is entirely overlapped by the pixel electrode.