Capacitor Sharing Surge Protection Circuit

• US 20100128407A1
• Filed: 01/28/2010
• Published: 05/27/2010
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MAGGIOLINO, Louis
• Granted Patent: US 8,027,138 B2
• Time in Patent Office: Days
• US Class Current: 361/119
• CPC Class Codes: H02H 1/0038 concerning the connection of the detecting means, e.g. for reducing their number
• CPC Class Codes: H02H 9/04 responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T

Abstract

A capacitor sharing surge protection circuit for protecting multiple ports from harmful energy surges, such as electrostatic discharge (ESD) and cable discharge events (CDE), is provided. The protection circuit includes a plurality of diodes with respective cathodes and anodes. Each anode of the plurality of diodes is coupled to one of the plurality of ports. A bypass capacitor is coupled between the cathodes of the plurality of diodes and ground. In an embodiment, a bulk capacitor is further coupled between the cathodes of the plurality of diodes and ground.

Claims

1. A data switch for use in a Power over Ethernet (PoE) communications system, comprising:

a plurality of Ethernet ports configured to communicate data and power between powered devices; and

a protection circuit, comprising;

a positive diode array comprising a first plurality of diodes that each include a cathode and an anode, wherein each anode of the first plurality of diodes is coupled to a single one of the plurality of Ethernet ports;

a positive surge bus coupled between the cathodes of the first plurality of diodes and a bulk capacitor;

a negative diode array comprising a second plurality of diodes that each include a cathode and an anode, wherein each cathode of the second plurality of diodes is coupled to a single one of the plurality of Ethernet ports; and

a negative surge bus coupled between the anodes of the second plurality of diodes and ground.

2. The data switch of claim 1, wherein the bulk capacitor is configured to provide a low impedance path to ground for low frequency surge events coupled to any one of the plurality of Ethernet ports.

3. The data switch of claim 2, wherein the bulk capacitor is comprised of a plurality of bypass capacitors coupled together in parallel.

4. The data switch of claim 1, wherein the positive diode array and the negative diode array are deposited on multiple substrates.

5. The data switch of claim 1, further comprising a transient voltage suppression (TVS) diode coupled between the positive surge bus and ground.

6. The data switch of claim 1, wherein at least one of the plurality of Ethernet ports includes a first transformer configured to transmit data to a powered device and a second transformer configured to receive data from a powered device.

7. The data switch of claim 6, wherein a center tap of the first transformer is coupled to an anode of one of the first plurality of diodes and a cathode of one of the second plurality of diodes.

8. The data switch of claim 6, wherein a center tap of the second transformer is coupled to an anode of one of the first plurality of diodes and a cathode of one of the second plurality of diodes.

9. A Power over Ethernet (PoE) protection circuit, comprising:

a positive diode array comprising a first plurality of diodes that each include a cathode and an anode, wherein each anode of the first plurality of diodes is coupled to a single one of a plurality of Ethernet ports;

a positive surge bus coupled between the cathodes of the first plurality of diodes and a bulk capacitor;

a negative diode array comprising a second plurality of diodes that each include a cathode and an anode, wherein each cathode of the second plurality of diodes is coupled to a single one of the plurality of Ethernet ports; and

a negative surge bus coupled between the anodes of the second plurality of diodes and ground.

10. The PoE protection circuit of claim 9, wherein the bulk capacitor is configured to provide a low impedance path to ground for low frequency surge events coupled to any one of the plurality of Ethernet ports.

11. The PoE protection circuit of claim 10, wherein the bulk capacitor is comprised of a plurality of bypass capacitors coupled together in parallel.

12. The PoE protection circuit of claim 9, wherein the positive diode array and the negative diode array are deposited on multiple substrates.

13. The PoE protection circuit of claim 9, further comprising a transient voltage suppression (TVS) diode coupled between the positive surge bus and ground.

14. The PoE protection circuit of claim 9, wherein at least one of the plurality of Ethernet ports includes a first transformer configured to transmit data to a powered device and a second transformer configured to receive data from a powered device.

15. The PoE protection circuit of claim 14, wherein a center tap of the first transformer is coupled to an anode of one of the first plurality of diodes and a cathode of one of the second plurality of diodes.

16. The PoE protection circuit of claim 14, wherein a center tap of the second transformer is coupled to an anode of one of the first plurality of diodes and a cathode of one of the second plurality of diodes.