METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICECIRCUIT DEVICE

• US 20100129974A1
• Filed: 11/20/2009
• Published: 05/27/2010
• Est. Priority Date: 11/26/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: MURATA, Shuhei, HAYASHI, Takeshi, FUTASE, Takuya
• Granted Patent: US 7,923,319 B2
• Time in Patent Office: Days
• US Class Current: 438/303
• CPC Class Codes: H01L 21/67167 surrounding a central transfer chamber
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.

Claims

1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

(a) forming a MISFET in a region in the vicinity of a first main surface of a semiconductor wafer,

the MISFET having;

(x1) source/drain regions disposed in a surface region of the first main surface;

(x2) a gate insulation film disposed over the first main surface;

(x3) a gate electrode disposed over the gate insulation film; and

(x4) a silicide film disposed over the source/drain regions;

(b) after the step (a), setting the semiconductor wafer over a first lower electrode in a first gas phase treatment chamber with the first main surface facing upward;

(c) after the step (b), while the semiconductor wafer being set over the first lower electrode grounded with the first main surface facing upward, carrying out a plasma treatment on the first main surface under a first gas atmosphere containing an inert gas as one of main components; and

(d) after the step (c), while the semiconductor wafer being set over the first lower electrode with the first main surface facing upward, forming a silicon nitride film over the first main surface by a CVD treatment.

2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the inert gas is an argon gas.

3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the first gas atmosphere substantially does not contain hydrogen.

4. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the first gas atmosphere substantially does not contain a hydrogen gas and an ammonia gas.

5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first gas atmosphere contains a nitrogen gas as one of main components.

6. The method for manufacturing a semiconductor integrated circuit device according to claim 1,

wherein the MISFET further has:

(x5) a sidewall insulation film disposed at the sidewall of the gate electrode; and

(x6) an extension region which is a semiconductor region disposed in a region under the sidewall insulation film, and

wherein the lower end width of the sidewall insulation film is smaller than the depth of the extension region.

7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps of:

(e) forming a silicon oxide film type premetal interlayer insulation film over the silicon nitride film;

(f) opening a contact hole in the premetal interlayer insulation film with the silicon nitride film as an etching stop film;

(g) after the step (f), etching the silicon nitride film, thereby to extend the contact hole to the top surface of the silicide film disposed over the source/drain regions;

(h) after the step (g), setting the semiconductor wafer over a second lower electrode in a second gas phase treatment chamber with the first main surface facing upward;

(i) after the step (h), while the semiconductor wafer being set over the second lower electrode grounded with the first main surface facing upward, carrying out a plasma treatment on the first main surface under a second gas atmosphere containing an inert gas as one of main components;

(j) after the step (i), while the semiconductor wafer being set over the second lower electrode grounded with the first main surface facing upward, forming a barrier metal film over the inner surface of the contact hole; and

(k) after the step (j), filling the contact hole with a metal containing tungsten as a main component.

8. The method for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps of:

(e) forming a silicon oxide film type premetal interlayer insulation film over the silicon nitride film;

(f) opening a contact hole in the premetal interlayer insulation film with the silicon nitride film as an etching stop film;

(g) after the step (f), etching the silicon nitride film, thereby to extend the contact hole to the top surface of the silicide film disposed over the source/drain regions;

(j) after the step (g), forming a barrier metal film over the inner surface of the contact hole; and

(k) after the step (j), filling the contact hole with a metal containing tungsten as a main component.

9. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the inert gas of the step (i) is an argon gas.

10. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the second gas atmosphere substantially does not contain hydrogen.

11. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the second gas atmosphere substantially does not contain a hydrogen gas and an ammonia gas.

12. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the second gas atmosphere substantially does not contain a nitrogen gas.

13. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

(a) forming a MISFET in a region in the vicinity of a first main surface of a semiconductor wafer,

the MISFET having;

(x1) source/drain regions disposed in a surface region of the first main surface;

(x2) a gate insulation film disposed over the first main surface;

(x3) a gate electrode disposed over the gate insulation film; and

(x4) a silicide film disposed over the source/drain regions;

(b) after the step (a), disposing the semiconductor wafer over a first lower electrode in a first gas phase treatment chamber with the first main surface facing upward;

(c) after the step (b), while the semiconductor wafer being set over the first lower electrode with the first main surface facing upward, carrying out a low bias plasma treatment with a self bias of the first lower electrode of 10 V or less on the first main surface under a first gas atmosphere containing an inert gas as one of main components; and

(d) after the step (c), while the semiconductor wafer being set over the first lower electrode with the first main surface facing upward, forming a silicon nitride film over the first main surface by a CVD treatment.

14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the inert gas is an argon gas.

15. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the first gas atmosphere substantially does not contain hydrogen.

16. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the first gas atmosphere substantially does not contain a hydrogen gas and an ammonia gas.

17. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the first gas atmosphere substantially contains a nitrogen gas as one of main components.

18. The method for manufacturing a semiconductor integrated circuit device according to claim 13,

wherein the MISFET further has:

(x5) a sidewall insulation film disposed at the sidewall of the gate electrode; and

(x6) an extension region which is a semiconductor region disposed in a region under the sidewall insulation film, and

wherein the lower end width of the sidewall insulation film is smaller than the depth of the extension region.

19. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

(a) forming a MISFET in a region in the vicinity of a first main surface of a semiconductor wafer,

the MISFET having;

(x1) source/drain regions disposed in a surface region of the first main surface;

(x2) a gate insulation film disposed over the first main surface;

(x3) a gate electrode disposed over the gate insulation film; and

(x4) a silicide film disposed over the source/drain regions;

(b) forming a silicon oxide film type premetal interlayer insulation film over the silicon nitride film;

(c) opening a contact hole in the premetal interlayer insulation film with the silicon nitride film as an etching stop film;

(d) after the step (c), etching the silicon nitride film, thereby to extend the contact hole to the top surface of the silicide film disposed over the source/drain regions;

(e) after the step (d), setting the semiconductor wafer over a lower electrode in a gas phase treatment chamber with the first main surface facing upward;

(f) after the step (e), while the semiconductor wafer being set over the lower electrode grounded with the first main surface facing upward, carrying out a plasma treatment on the first main surface under a gas atmosphere containing an inert gas as one of main components;

(g) after the step (f), while the semiconductor wafer being set over the first lower electrode with the first main surface facing upward, forming a barrier metal film over the inner surface of the contact hole; and

(h) after the step (g), filling the contact hole with a metal containing tungsten as a main component.

20. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein the inert gas is an argon gas.

21. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein the gas atmosphere substantially does not contain hydrogen.

22. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein the gas atmosphere substantially does not contain a nitrogen gas.