SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
First Claim
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1. A manufacturing method of a semiconductor device comprising the steps of:
- (a) forming a plurality of wiring trenches in a first insulating film on a semiconductor substrate;
(b) forming a first conductive film on the first insulating film including respective insides of the plurality of wiring trenches;
(c) forming wirings formed of the first conductive film inside the respective wiring trenches by removing a portion of the first conductive film outside the wiring trenches by CMP;
(d) forming a first barrier insulating film on the first insulating film and the wirings;
(e) forming a reservoir position by removing the first barrier insulating film and the first insulating film except portions of the first barrier insulating film and the first insulating film in lower regions and their peripheral regions of through holes, which are formed later and from which upper surfaces of the wirings are exposed;
(f) forming a second barrier insulating film on the first barrier insulating film and side and upper surfaces of the wirings so that the second barrier insulating film on spaces between the wirings is made thinner than the second barrier insulating film on the wirings;
(g) forming a second insulating film on the second barrier insulating film while leaving gaps in space regions between the wirings from which the first barrier insulating film and the first insulating film have been removed;
(h) forming through holes penetrating through the first barrier insulating film, the second barrier insulating film and the second insulating film on an upper portion of the wirings; and
(i) forming a second conductive film inside the through holes.
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Abstract
Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP.
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Citations
28 Claims
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1. A manufacturing method of a semiconductor device comprising the steps of:
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(a) forming a plurality of wiring trenches in a first insulating film on a semiconductor substrate; (b) forming a first conductive film on the first insulating film including respective insides of the plurality of wiring trenches; (c) forming wirings formed of the first conductive film inside the respective wiring trenches by removing a portion of the first conductive film outside the wiring trenches by CMP; (d) forming a first barrier insulating film on the first insulating film and the wirings; (e) forming a reservoir position by removing the first barrier insulating film and the first insulating film except portions of the first barrier insulating film and the first insulating film in lower regions and their peripheral regions of through holes, which are formed later and from which upper surfaces of the wirings are exposed; (f) forming a second barrier insulating film on the first barrier insulating film and side and upper surfaces of the wirings so that the second barrier insulating film on spaces between the wirings is made thinner than the second barrier insulating film on the wirings; (g) forming a second insulating film on the second barrier insulating film while leaving gaps in space regions between the wirings from which the first barrier insulating film and the first insulating film have been removed; (h) forming through holes penetrating through the first barrier insulating film, the second barrier insulating film and the second insulating film on an upper portion of the wirings; and (i) forming a second conductive film inside the through holes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A manufacturing method of a semiconductor device comprising the steps of:
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(a′
) forming a plurality of wiring trenches in a first insulating film and a second insulating film on a semiconductor substrate;(b′
) forming a first conductive film on the second insulating film including respective insides of the plurality of wiring trenches;(c′
) forming wirings formed of the first conductive film inside the respective wiring trenches by removing a portion of the first conductive film outside the wiring trenches by CMP;(d′
) forming a first barrier insulating film on the second insulating film and the wirings;(e′
) forming a reservoir position by removing the first barrier insulating film and the second insulating film except portions of the first barrier insulating film and the second insulating film in lower regions and their peripheral regions of through holes, which are formed later and from which upper surfaces of the wirings are exposed;(f) forming a second barrier insulating film on the first barrier insulating film and side and upper surfaces of the wirings so that the second barrier insulating film on spaces between the wirings is made thinner than the second barrier insulating film on the wirings; (g′
) forming a third insulating film on the second barrier insulating film while leaving gaps in space regions between the wirings from which the first barrier insulating film and the second insulating film have been removed;(h′
) forming through holes penetrating through the first barrier insulating film, the second barrier insulating film and the third insulating film on an upper portion of the wirings; and(i) forming a second conductive film inside the through holes. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification
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Current AssigneeKokusai Electric Corp.
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Original AssigneeHitachi, Ltd.
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InventorsNOGUCHI, Junji
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current438/627
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CPC Class CodesH01L 21/02697 Forming conducting material...H01L 21/76811 involving multiple stacked ...H01L 21/7682 the dielectric comprising a...H01L 21/76834 formation of thin insulatin...H01L 21/76835 Combinations of two or more...H01L 23/5222 Capacitive arrangements or ...H01L 23/53295 Stacked insulating layersH01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
