Method and Apparatus for Measuring Transmission and Reception in Electronic Devices

• US 20100131214A1
• Filed: 11/26/2008
• Published: 05/27/2010
• Est. Priority Date: 11/26/2008
• Status: Abandoned Application

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Antles, Thomas II, Seely, Dan
• Application Number:
  US12/324,669
• Publication Number:
  US 20100131214A1
• Time in Patent Office: Days
• US Class Current: 702/58
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22

Abstract

In a representative embodiment, an apparatus comprises a host subsystem comprising a user interface and configured to receive a plurality of parameters; and a processor comprising a hardware interface and configured calculate hardware states based on at least a subset of the plurality of parameters. The apparatus also comprises a first subsystem comprising a hardware control processor adapted to configure first hardware based on the calculated hardware states; and a second subsystem comprising second hardware and a second hardware control processor adapted to configure the second hardware based on the calculated hardware states. The apparatus also comprises a data converter configured to provide data directly to the host subsystem.

Claims

1. A method, comprising:

providing a plurality of parameters to an apparatus;

configuring hardware based on a subset of the plurality of parameters;

conducting a first measurement at a first frequency and a first power level during a first measurement step;

conducting a second measurement at the first frequency and a second power level during a second measurement step; and

during the second measurement, obtaining data from the first measurement step, and computing a plurality of measurement results based on the data.

2. A method as claimed in claim 1, further comprising, after the obtaining, providing the data directly to a host processor.

3. A method as claimed in claim 1, wherein the parameters further comprise hardware state settings.

4. A method as claimed in claim 1, wherein the first and second measurements each comprise a measurement on an uplink of a device under test (DUT), and the method further comprises:

substantially simultaneously with either the first measurement, or the second measurement, or both the first and second measurements, conducting a third measurement at a second frequency and a second power level during a third measurement step, wherein the third measurement comprises a measurement on a downlink of the DUT.

5. A method as claimed in claim 1, wherein the first and second measurement steps occur during a first measurement period and another subset of the plurality of parameters comprises parameters for a second measurement period.

6. A method as claimed in claim 1, after the providing the plurality of parameters, setting a trigger to initiate the first measurement.

7. A method as claimed in claim 2, further comprising, after the obtaining and before the providing, converting the data to digital data;

and the providing further comprises;

providing the digital data from a first memory to a second memory by direct memory access (DMA).

8. A method as claimed in claim 1, wherein first measurement step and the second measurement step each comprise respective step lengths and trigger delays and the trigger delays are less than approximately 20% of a duration of the step length.

9. A method as claimed in claim 2, wherein the providing the hardware state settings further comprises:

receiving a plurality of frequencies and power levels; and

calculating operating values for hardware required for each frequency and power level.

10. An apparatus, comprising:

a host subsystem comprising a user interface and configured to receive a plurality of parameters;

a processor comprising a hardware interface and configured calculate hardware states based on at least a subset of the plurality of parameters;

a first subsystem comprising a hardware control processor adapted to configure first hardware based on the calculated hardware states;

a second subsystem comprising second hardware and a second hardware control processor adapted to configure the second hardware based on the calculated hardware states; and

a data converter configured to provide data directly to the host subsystem.

11. An apparatus as claimed in claim 10, wherein the data converter further comprises a measurement sample collector.

12. An apparatus as claimed in claim 10, wherein the data converter further comprises a direct memory access (DMA) module configured to transfer the data directly to a memory in the host processor.

13. An apparatus as claimed in claim 10, wherein the first subsystem further comprises a source subsystem and the first hardware comprises source hardware, and the source subsystem further comprises a source memory configured to store a subset of the calculated hardware states and to replace an expired hardware state with a new hardware state from the subset of the plurality hardware states.

14. An apparatus as claimed in claim 10, wherein the second subsystem further comprises a receiver subsystem and the second hardware comprises receiver hardware, and the receiver subsystem comprises a receiver memory configured to store a subset of the calculated hardware states and to replace an expired hardware state with a new hardware state from the subset of the plurality hardware states.

15. An apparatus as claimed in claim 11, wherein the data converter further comprises a dual ported memory controller configured to collect data from a current measurement and to substantially simultaneously transfer data from a previous measurement directly to the host subsystem.

16. An apparatus as claimed in claim 12, wherein the data converter is configured to receive a trigger from a user and to populate a memory with a plurality of measurement triggers based on the received trigger.

17. An apparatus as claimed in claim 11, wherein the data converter is connected to a device under test (DUT).

18. An apparatus as claimed in claim 17, wherein first data are transmitted to the DUT and second data are received from the DUT substantially simultaneously.

19. An apparatus as claimed in claim 18, wherein the DUT comprises a radio frequency (RF) device.

20. A system, comprising:

a system interface;

apparatus connected to the system interface, the apparatus comprising;

a host subsystem comprising a user interface and configured to receive a plurality of parameters;

a processor comprising a hardware interface and configured calculate hardware states based on at least a subset of the plurality of parameters;

a first subsystem comprising a hardware control processor adapted to configure first hardware based on the calculated hardware states;

a second subsystem comprising second hardware and a second hardware control processor adapted to configure the second hardware based on the calculated hardware states; and

a data converter configured to provide data directly to the host subsystem.

21. A system as claimed in claim 20, wherein data converter comprises a measurement sample collector configured to provide data directly to the host subsystem.

22. A system as claimed in claim 21, wherein the data converter further comprises a direct memory access (DMA) module configured to transfer the data directly to a memory in the host processor.

23. A system as claimed in claim 20, wherein the first subsystem comprises a source subsystem and the first hardware comprises a receiver hardware, and the source subsystem comprises a source memory configured to store a subset of the calculated hardware states and to replace an expired hardware state with a new hardware state from the subset of the plurality hardware states.

24. A system as claimed in claim 20, wherein the second subsystem comprises a receiver subsystem and the second hardware comprises receiver hardware, wherein the receiver subsystem comprises a receiver memory configured to store a subset of the calculated hardware states and to replace an expired hardware state with a new hardware state from the subset of the plurality hardware states.

25. A system as claimed in claim 21, wherein the data converter further comprises a dual ported memory controller configured to collect data from a current measurement and to substantially simultaneously transfer data from a previous measurement directly to the host subsystem.

26. A system as claimed in claim 22, wherein the data converter is configured to receive a trigger from a user and to populate a memory with a plurality of measurement triggers based on the received trigger.

27. A system as claimed in claim 21, wherein the data converter is connected to a device under test (DUT).

28. A system as claimed in claim 27, wherein first data are transmitted to the DUT and second data are received from the DUT substantially simultaneously.