CACHE MEMORY BYPASS IN A MULTI-CORE PROCESSOR (MCP)

• US 20100131717A1
• Filed: 11/21/2008
• Published: 05/27/2010
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Kyndryl Incorporated
• Original Assignee: International Business Machines Corporation
• Inventors: Risi, Eugene B., Dumarot, Dan P., Kim, Moon J., Kim, Daeik, Duvalsaint, Karl J.
• Granted Patent: US 9,886,389 B2
• Time in Patent Office: Days
• US Class Current: 711/138
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc

Abstract

This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Claims

1. A bypass memory system, comprising:

a first memory unit mounted on a bus;

a first cache manager coupled to the first memory unit; and

a second memory unit mounted on the bus, the first cache manager being operable to;

receive a request, bypass the first memory unit with the request, and send the request to the second memory unit.

2. The bypass memory system of claim 1, the first memory unit and the second memory unit comprising virtualized cache memory units.

3. The bypass memory system of claim 1, further comprising a second cache manager coupled to the second memory unit, the second cache manager being operable to receive the request from the first cache manager, and send the request to the second memory unit.

4. The bypass memory system of claim 3, the second cache manager being further operable to receive an additional request, bypass the second memory unit with the additional request, and send the additional request to at least one of the following:

the first memory unit;

or a third memory unit.

5. The bypass memory system of claim 3, further comprising:

a first set of sub-memory units coupled to the first cache manager; and

a first set of sub-processing elements coupled to the first set of sub-memory units.

6. The bypass memory system of claim 5, further comprising:

a second set of sub-memory units coupled to the second cache manager; and

a second set of sub-processing elements coupled to the second set of sub-memory units.

7. The bypass memory system of claim 1, the bus being coupled to a main controller.

8. The bypass memory system of claim 1, the first cache manager bypassing the first memory unit when the first memory unit is at least one of the following:

exhibiting a yield below a predetermined threshold;

or inoperable.

9. The bypass memory system of claim 1, the first mounting unit being coupled to an input and an output of the first memory unit.

10. A cache bypass system, comprising:

a first cache memory unit mounted on a bus;

a first cache manager coupled to an input and an output of the first cache memory unit;

a first set of sub-cache memory units coupled to the first cache manager;

a second cache memory unit mounted on the bus;

a second cache manager coupled to an input and an output of the second cache memory unit; and

a second set of sub-cache memory units coupled to the second cache manager, the first cache manager and the second cache manager each being operable to;

receive a request, bypass a cache memory unit to which it is coupled, and send the request to different cache memory unit.

11. The cache bypass system of claim 10, further comprising a first set of sub-processing elements coupled to the first set of sub-cache memory units.

12. The cache bypass system of claim 10, further comprising a second set of sub-processing elements coupled to the second set of sub-cache memory units.

13. The cache bypass system of claim 10, the bus being coupled to a main controller.

14. A memory bypass method, comprising:

receiving a first request on a cache manager, the first cache manager being coupled to a first memory unit, the first memory unit being coupled to a bus; and

bypassing the first memory unit by sending the first request from the first cache manager to a second cache manager, the second cache manager being coupled to a second memory unit, the second memory unit being coupled to the bus.

15. The memory bypass method of claim 14, the first request being received from a first set of sub-memory units coupled to the first memory unit.

16. The memory bypass method of claim 14, further comprising:

receiving a second request on the second cache manager; and

bypassing the second memory unit by sending the second request from the second cache manager to at least one of the following;

the first cache manager;

or a third cache manager.

17. The memory bypass method of claim 15, the second request being received from a second set of sub-memory units coupled to the second memory unit.

18. The memory bypass method of claim 17, the first memory unit, the first set of sub-memory units, the second memory unit, and the second set of sub-memory units being cache memory units.

19. The memory bypass method of claim 14, further comprising sending a response to the first request from the second memory unit to an originator of the request.

20. The memory bypass method of claim 19, the response being sent via the second cache manager.