System and Method of Dynamically Switching Queue Threshold

• US 20100131783A1
• Filed: 11/24/2008
• Published: 05/27/2010
• Est. Priority Date: 11/24/2008
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Weng, Chih-Hao, Yeh, Ta-Jung
• Granted Patent: US 8,412,866 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method of dynamically switching the threshold of a data queue, such as FIFO, is disclosed. The data queue has a first threshold and a second threshold, wherein the first threshold is greater than the second threshold. The data queue is dynamically switched between the first threshold and the second threshold according to different power state of a central processing unit (CPU). A system memory is requested to fill the data queue with data whenever amount of the data queue is less than the switched first/second threshold.

Claims

1. A system of dynamically switching queue threshold, comprising:

a data queue, having a first threshold and a second threshold, the data queue being dynamically switched between the first threshold and the second threshold according to different power state of a central processing unit (CPU), wherein the first threshold is greater than the second threshold;

wherein a system memory is requested to fill the data queue with data whenever amount of the data queue is less than the switched first/second threshold.

2. The system of claim 1, wherein the data queue is changed from the first threshold to the second threshold when the CPU changes from a first power state to a second power state, wherein the second power state saves more power than the first power state.

3. The system of claim 2, wherein the data queue has the first threshold when the CPU is in C0/C2 state;

and the data queue has the second threshold when the CPU is in C3/C4 state, wherein the states C0, C2, C3 and C4 are defined in Advanced Configuration and Power Interface (ACPI) specification.

4. The system of claim 3, further comprising a power management unit (PMU) for controlling the power state of the CPU.

5. The system of claim 2, wherein the second threshold is equal to:

(data unit of transportation)*[(time required to change from the second/first power state into the first/second power state)/(time unit of transportation)]+n*(data unit of transportation)

where integer n is not less than 0.

6. The system of claim 5, wherein the n is controlled by three bits of a register, and n may be any integer between 0 and 7 inclusively.

7. The system of claim 1, wherein the data queue is first-in first-out buffer (FIFO), the system further including at least one direct memory access engine (DMA), wherein the FIFO corresponds to the at least one DMA, and the system memory is requested to fill the data queue via the at least one DMA.

8. The system of claim 7, further comprising a HDA link for connecting the DMA to one or more coder/decoders (codecs).

9. A method of dynamically switching queue threshold, comprising:

dynamically switching a data queue between a first threshold and a second threshold according to different power state of a central processing unit (CPU), wherein the first threshold is greater than the second threshold;

wherein a system memory is requested to fill the data queue with data whenever amount of the data queue is less than the switched first/second threshold.

10. The method of claim 9, wherein the data queue is changed from the first threshold to the second threshold when the CPU changes from a first power state to a second power state, wherein the second power state saves more power than the first power state.

11. The method of claim 10, wherein the data queue has the first threshold when the CPU is in C0/C2 state;

and the data queue has the second threshold when the CPU is in C3/C4 state, wherein the states C0, C2, C3 and C4 are defined in Advanced Configuration and Power Interface (ACPI) specification.

12. The method of claim 11, further comprising a step of using a power management unit (PMU) for controlling the power state of the CPU.

13. The method of claim 10, wherein the second threshold is equal to:

(data unit of transportation)*[(time required to change from the second/first power state into the first/second power state)/(time unit of transportation)]+n*(data unit of transportation)

where integer n is not less than 0.

14. The method of claim 13, wherein the n is controlled by three bits of a register, and n may be any integer between 0 and 7 inclusively.

15. The method of claim 9, wherein the method is adaptable to a High Definition Audio (HDA) system, and the data queue is first-in first-out buffer (FIFO), the system further including a HDA controller that includes at least one direct memory access engine (DMA), wherein the FIFO corresponds to the at least one DMA.

16. The method of claim 15, wherein the CPU changes to C0/C2 state, whenever the HDA controller becomes inactive, the CPU is in C3/C4 state, and an input device inputs data, wherein the states C0, C2, C3 and C4 are defined in Advanced Configuration and Power Interface (ACPI) specification.

17. The method of claim 15, wherein the FIFO uses the second threshold, whenever the HDA controller becomes active and the HDA controller detects that the CPU is in C3/C4 state, wherein states C3 and C4 are defined in Advanced Configuration and Power Interface (ACPI) specification.

18. The method of claim 17, when the second threshold is greater than the first threshold, the FIFO continues to use the first threshold.

19. The method of claim 18, wherein the CPU changes to C0/C2 state, whenever an input device inputs data or amount of the FIFO is less than the second threshold, wherein states C0 and C2 are defined in Advanced Configuration and Power Interface (ACPI) specification.

20. The method of claim 17, wherein a power management unit (PMU) issues a signal PMU_C3/C4 to notify the HDA controller of the C3/C4 state of the CPU.