MEMORY DEVICE WITH INTERNAL SIGNAP PROCESSING UNIT

• US 20100131827A1
• Filed: 04/16/2008
• Published: 05/27/2010
• Est. Priority Date: 05/12/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Perlmutter, Uri, Sokolov, Dotan, Sommer, Naftali
• Granted Patent: US 8,429,493 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code

Abstract

A method for operating a memory (36) includes storing data in a plurality of analog memory cells (40) that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry (48) that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller (28), which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

Claims

1. A method for operating a memory, comprising:

storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells;

after storing the data, reading multiple output storage values from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets;

preprocessing the multiple output sets of the output storage values by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data; and

providing the preprocessed data to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data stored in the group of the analog memory cells responsively to the preprocessed data.

2. The method according to claim 1, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein preprocessing the multiple output sets comprises computing ECC metrics based on the read output storage values, and wherein providing the preprocessed data comprises providing the ECC metrics to the memory controller, so as to enable the memory controller to decode the ECC using the metrics.

3. The method according to claim 1, wherein preprocessing the multiple output sets and providing the preprocessing data comprise:

computing initial values of the ECC metrics responsively to a subset of the output storage values read from each of the analog memory cells, and providing the initial values to the memory controller; and

responsively to a failure of the memory controller in decoding the ECC using the initial values, extending the subset with at least one additional output storage value from each of the analog memory cells, re-computing the ECC metrics responsively to the extended subset, and providing the re-computed ECC metrics to the memory controller.

4. The method according to claim 3, wherein the initial values comprise hard metric values that are based on a single output storage value from each of the analog memory cells, and wherein the re-computed ECC metrics comprise soft metrics that are based on multiple output storage values read from each of the analog memory cells.

5. The method according to claim 3, and comprising receiving a notification regarding the failure from the memory controller, and re-computing the ECC metrics responsively to the notification.

6. The method according to claim 5, wherein receiving the notification comprises receiving information that characterizes the failure from the memory controller, and wherein re-computing the ECC metrics comprises modifying the ECC metrics based on the information.

7. The method according to claim 1, wherein preprocessing the multiple output sets comprises estimating a statistical property of the output storage values, and wherein providing the preprocessed data comprises providing the estimated statistical property to the memory controller.

8. The method according to claim 7, wherein the statistical property comprises one of a mean of the output storage values, a variance of the output storage values, a number of the analog memory cells in the group whose output storage values are within a given range of values, a Probability Density Function (PDF) of the output storage values, a histogram of the output storage values, a Cumulative Distribution Function (CDF) of the output storage values and an inverse CDF of the output storage values.

9. The method according to claim 1, wherein preprocessing the multiple output sets comprises modifying the read thresholds responsively to the read output storage values.

10. The method according to claim 9, and comprising receiving from the memory controller a notification regarding a failure to reconstruct the data, and modifying the read thresholds responsively to the notification.

11. The method according to claim 10, wherein receiving the notification comprises receiving information that characterizes the failure from the memory controller, and wherein modifying the read thresholds comprises modifying the thresholds based on the information.

12. The method according to claim 1, wherein the multiple output sets of the output storage values have a first size, and wherein the preprocessed data has a second size that is smaller than the first size.

13. The method according to claim 1, wherein preprocessing the multiple output sets comprises accepting one or more parameters from the memory controller, and preprocessing the output sets responsively to the parameters.

14. A method for operating a memory, comprising:

storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing first storage values to a first group of the analog memory cells;

after storing the data, reading from the memory cells in the first group second storage values, at least some of which differ from the respective first storage values due to distortion;

receiving a request from a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die, to cancel the distortion in the second storage values; and

responsively to the request, reading third storage values from a second group of the analog memory cells, and canceling the distortion in the second storage values based on the third storage values using circuitry that is fabricated on the first semiconductor die, so as to enable the memory controller to reconstruct the data.

15. The method according to claim 14, wherein reading the second storage values comprises reading multiple sets of the second storage values using respective, different read thresholds, and wherein canceling the distortion comprises selecting, responsively to the third storage values, a second storage value that contains a minimal level of the distortion in each of the sets.

16. The method according to claim 14, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein reading the second storage values comprises reading multiple sets of the second storage values using respective, different read thresholds, and wherein canceling the distortion comprises combining the multiple sets of the second storage values responsively to the third storage values to produce soft metrics, so as to enable decoding of the ECC using the soft metrics.

17. The method according to claim 14, wherein receiving the request comprises receiving from the memory controller a notification regarding a failure to reconstruct the data in the presence of the distortion.

18. The method according to claim 14, wherein reading the third storage values and canceling the distortion comprise:

initially reading the third storage values from only some of the analog memory cells in the second group and canceling the distortion based on the initially-read third storage values; and

responsively to a failure of the memory controller to reconstruct the data, reading at least one additional third storage value from at least one additional analog memory cell in the second group, and re-canceling the distortion responsively to the read third storage values, including the at least one additional third storage value.

19. The method according to claim 14, wherein canceling the distortion comprises accepting one or more parameters from the memory controller, and canceling the distortion responsively to the parameters.

20. A method for data storage, comprising:

storing data in a memory device comprising a plurality of analog memory cells that are fabricated on a first semiconductor die by writing first storage values to a group of the analog memory cells;

after storing the data, reading from the memory cells in the group second storage values;

performing a preprocessing operation on the read second storage values by processing circuitry that is fabricated on the first semiconductor die, so as to produce preprocessed data;

providing the preprocessed data to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data;

accepting in the processing circuitry feedback from the memory controller regarding reconstruction of the data; and

modifying the preprocessing operation of the processing circuitry responsively to the feedback.

21. The method according to claim 20, wherein the feedback comprises information regarding past usage of read thresholds.

22. A method for data storage, comprising:

storing data in a memory device comprising a plurality of analog memory cells by writing first storage values to a group of the analog memory cells;

after storing the data, receiving in the memory device a request from a memory controller to retrieve the data;

responsively to the request, reading from the memory cells in the group second storage values, and invoking an auxiliary computation unit to preprocess the second storage values to produce preprocessed data; and

providing the preprocessed data to the memory controller, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

23. A method for data storage, comprising:

storing data in a memory device that includes a plurality of analog memory cells by writing first storage values to a group of the analog memory cells;

after storing the data, receiving in the memory device a request from a memory controller to retrieve the data;

accepting in the memory device one or more analog control signals, which are produced and applied by the memory controller so as to specify voltages or currents that are to be used by the memory device in retrieving the data from the analog memory cells;

responsively to the request, setting the specified voltages or currents, and reading from the memory cells in the group second storage values using the set voltages or currents; and

providing the second storage values to the memory controller, so as to reconstruct the data.

24. A memory device, comprising:

a first semiconductor die;

a plurality of analog memory cells, which are fabricated on the first semiconductor die; and

processing circuitry, which is fabricated on the first semiconductor die and is operative to store data in the plurality of the analog memory cells by writing input storage values to a group of the analog memory cells, to read, after storing the data, multiple output storage values from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets, to preprocess the multiple output sets of the output storage values so as to produce preprocessed data, and to provide the preprocessed data to a memory controller that is fabricated on a second semiconductor die different from the first semiconductor die, so as to reconstruct the data stored in the group of the analog memory cells responsively to the preprocessed data.

25. The memory device according to claim 24, wherein the data is encoded with an Error Correction Code (ECC), and wherein the processing circuitry is operative to compute ECC metrics based on the read output storage values and to provide the ECC metrics to the memory controller, so as to enable the memory controller to decode the ECC using the metrics.

26. The memory device according to claim 24, wherein the processing circuitry is operative to compute initial values of the ECC metrics responsively to a subset of the output storage values read from each of the analog memory cells, to provide the initial values to the memory controller and, responsively to a failure of the memory controller in decoding the ECC using the initial values, to extend the subset with at least one additional output storage value from each of the analog memory cells, to re-compute the ECC metrics responsively to the extended subset, and to provide the re-computed ECC metrics to the memory controller.

27. The memory device according to claim 26, wherein the initial values comprise hard metric values that are based on a single output storage value from each of the analog memory cells, and wherein the re-computed ECC metrics comprise soft metrics that are based on multiple output storage values read from each of the analog memory cells.

28. The memory device according to claim 26, wherein the processing circuitry is operative to receive a notification regarding the failure from the memory controller, and to re-compute the ECC metrics responsively to the notification.

29. The memory device according to claim 28, wherein the processing circuitry is operative to receive information that characterizes the failure from the memory controller, and to modify the ECC metrics based on the information.

30. The memory device according to claim 24, wherein the processing circuitry is operative to estimate a statistical property of the output storage values and to provide the estimated statistical property to the memory controller.

31. The memory device according to claim 30, wherein the statistical property comprises one of a mean of the output storage values, a variance of the output storage values, a number of the analog memory cells in the group whose output storage values are within a given range of values, a Probability Density Function (PDF) of the output storage values, a histogram of the output storage values, a Cumulative Distribution Function (CDF) of the output storage values and an inverse CDF of the output storage values.

32. The memory device according to claim 24, wherein the processing circuitry is operative to modify the read thresholds responsively to the read output storage values.

33. The memory device according to claim 32, wherein the processing circuitry is operative to receive from the memory controller a notification regarding a failure to reconstruct the data, and to modify the read thresholds responsively to the notification.

34. The memory device according to claim 33, wherein the processing circuitry is operative to receive information that characterizes the failure from the memory controller, and to modify the thresholds based on the information.

35. The memory device according to claim 24, wherein the multiple output sets of the output storage values have a first size, and wherein the preprocessed data has a second size that is smaller than the first size.

36. The memory device according to claim 24, wherein the processing circuitry is operative to accept one or more parameters from the memory controller, and to preprocess the output sets responsively to the parameters.

37. A memory device, comprising:

a first semiconductor die;

a plurality of analog memory cells, which are fabricated on the first semiconductor die; and

processing circuitry, which is fabricated on the first semiconductor die and is operative to store data in the plurality of analog memory cells by writing first storage values to a first group of the analog memory cells, to read from the memory cells in the first group, after storing the data, second storage values, at least some of which differ from the respective first storage values due to distortion, to receive from a memory controller, which is fabricated on a second semiconductor die different from the first semiconductor die, a request to cancel the distortion in the second storage values, to read responsively to the request third storage values from a second group of the analog memory cells, and to cancel the distortion in the second storage values based on the third storage values, so as to enable the memory controller to reconstruct the data.

38. The memory device according to claim 37, wherein the processing circuitry is operative to read multiple sets of the second storage values using respective, different read thresholds, and to cancel the distortion by selecting, responsively to the third storage values, a second storage value that contains a minimal level of the distortion in each of the sets.

39. The memory device according to claim 37, wherein the data is encoded with an Error Correction Code (ECC), and wherein the processing circuitry is operative to read multiple sets of the second storage values using respective, different read thresholds, and to cancel the distortion by combining the multiple sets of the second storage values responsively to the third storage values to produce soft metrics, so as to enable decoding of the ECC using the soft metrics.

40. The memory device according to claim 37, wherein the request comprises a notification from the memory controller regarding a failure to reconstruct the data in the presence of the distortion.

41. The memory device according to claim 37, wherein the processing circuitry is operative to initially read the third storage values from only some of the analog memory cells in the second group, to cancel the distortion based on the initially-read third storage values, to read, responsively to a failure of the memory controller to reconstruct the data, at least one additional third storage value from at least one additional analog memory cell in the second group, and to re-cancel the distortion responsively to the read third storage values, including the at least one additional third storage value.

42. The memory device according to claim 37, wherein the processing circuitry is operative to accept one or more parameters from the memory controller, and to cancel the distortion responsively to the parameters.

43. A memory device, comprising:

a first semiconductor die;

a plurality of analog memory cells, which are fabricated on the first semiconductor die; and

processing circuitry, which is fabricated on the first semiconductor die and is operative to store data in the plurality of analog memory cells by writing first storage values to a group of the analog memory cells, to read second storage values from the memory cells in the group after storing the data, to perform a preprocessing operation on the read second storage values so as to produce preprocessed data, to provide the preprocessed data to a memory controller fabricated on a second semiconductor die that is different from the first semiconductor die so as to enable the memory controller to reconstruct the data responsively to the preprocessed data, to accept feedback from the memory controller regarding reconstruction of the data, and to modify the preprocessing operation responsively to the feedback.

44. The memory device according to claim 43, wherein the feedback comprises information regarding past usage of read thresholds.

45. A data storage apparatus, comprising:

a memory device, comprising;

a plurality of analog memory cells; and

processing circuitry, which is operative to store data by writing first storage values to a group of the analog memory cells, and to retrieve the data by reading second storage values from the analog memory cells in the group; and

an auxiliary computation unit, which is coupled to preprocess the second storage values read from the analog memory cells to produce preprocessed data,

wherein the processing circuitry is operative to receive, after storing the data, a request from a memory controller to retrieve the data, to read the second storage values from the memory cells in the group responsively to the request, to invoke the auxiliary computation unit to preprocess the read second storage values so as to produce the preprocessed data, and to provide the preprocessed data to the memory controller.

46. A memory device, comprising:

a plurality of analog memory cells; and

processing circuitry, which is operative to store data by writing first storage values to a group of the analog memory cells, to receive, after storing the data, a request from a memory controller to retrieve the data, to accept from the memory controller one or more analog control signals, which specify voltages or currents that are to be used by the processing circuitry in retrieving the data from the analog memory cells, to set the specified voltages or currents responsively to the request, to read from the memory cells in the group second storage values using the set voltages or currents, and to provide the second storage values to the memory controller.