Protecting Isolated Secret Data of Integrated Circuit Devices

• US 20100132048A1
• Filed: 11/26/2008
• Published: 05/27/2010
• Est. Priority Date: 11/26/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jackowski, Stefan P., Hall, William E.
• Granted Patent: US 10,452,844 B2
• Time in Patent Office: Days
• US Class Current: 726/27
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 21/81 by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen

Abstract

A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.

Claims

1. A circuit arrangement for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device, the circuit arrangement comprising:

a clock circuit being responsive to an external clock signal;

a security state machine configured to control a security state of the integrated circuit device, wherein the security state machine is isolated from the clock circuit of the integrated circuit device; and

a master secret circuit in communication with the security state machine and configured to control access to the master secret data, wherein the master secret circuit is isolated from the clock circuit of the integrated circuit device, and wherein the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data.

2. The circuit arrangement of claim 1, wherein the security state machine is configured to reset the master secret circuit to selectively erase the portion of the master secret data.

3. The circuit arrangement of claim 1, further comprising:

at least one shadow register in communication with the master secret circuit and configured to capture at least a portion of the master secret data from, and communicate at least a portion of new master secret data to, the master secret circuit.

4. The circuit arrangement of claim 1, further comprising:

at least one shadow register in communication with the security state machine and configured to advance the security state of the integrated circuit device.

5. The circuit arrangement of claim 4, wherein advancing the security state of the integrated circuit includes an advance selected from the group consisting of an advance from a null security state to an initialized security state, an advance from the initialized security state to a secured security state, or an advance from the secured security state to a triggered security state.

6. The circuit arrangement of claim 1, further comprising:

a tamper event circuit in communication with the security state machine and configured to detect a tamper event of the integrated circuit device, wherein the security state machine is responsive to the tamper event circuit to change the security state of the integrated circuit device from a secured security state to a triggered security state in the event of the tamper event.

7. The circuit arrangement of claim 1, further comprising:

a power-on sense circuit in communication with the security state machine and configured to monitor a power signal to the at least one persistent region of the integrated circuit device, wherein the security state machine is responsive to the power-on sense circuit to change the security state of the integrated device to a triggered security state in response to the power-on sense circuit determining that the power signal is being initially supplied to the at least one persistent region.

8. The circuit arrangement of claim 1, further comprising:

a power-on reset circuit in communication with the security state machine and configured to detect a reset of the integrated circuit device, wherein the security state machine is responsive to the power-on reset circuit to change the security state of the integrated circuit device from a triggered security state to a null security state in the event of the reset of the integrated circuit device.

9. The circuit arrangement of claim 1, wherein the security state machine is configured to reset the master secret circuit to selectively erase the portion of the master secret data in response to changing the security state of the integrated circuit device to a triggered security state.

10. The circuit arrangement of claim 1, wherein the security state machine is configured to reset the master secret circuit to selectively erase the portion of the master secret data in response to changing the security state of the integrated circuit device to a null security state.

11. The circuit arrangement of claim 1, wherein the master secret data includes data selected from the group consisting of a master key, a boot record, a file record, and combinations thereof.

12. The circuit arrangement of claim 1, wherein the security state machine is isolated from the clock circuit to inhibit access to the master secret data in the event of a variance of the clock circuit.

13. A processing unit comprising the circuit arrangement of claim 1.

14. A computing system comprising the circuit arrangement of claim 1.

15. A method of controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device, the integrated circuit device of the type that includes a security state machine, a master secret circuit, and a clock circuit responsive to an external clock signal, wherein the security state machine and master secret circuit are isolated from the clock circuit, the method comprising:

controlling a security state of the integrated circuit device with the security state machine; and

in response to changing the security state of the integrated circuit device to a triggered security state or a null security state, selectively erasing at least a portion of the master secret data with the master secret circuit.

16. The method of claim 15, further comprising:

controlling access of at least one shadow register to the master secret data, wherein the at least one shadow register is configured to capture the master secret data from, and communicate new master secret data to, the master secret circuit.

17. The method of claim 16, wherein controlling the security state of the integrated circuit device includes:

detecting a tamper event; and

in response to detecting the tamper event, changing the security state of the integrated circuit device from a secured security state to the triggered security state.

18. The method of claim 15, wherein controlling the security state of the integrated circuit device includes:

detecting a reset of the integrated circuit device; and

in response to detecting the reset of the integrated circuit device, changing the security state of the integrated circuit device from the triggered security state to the null security state.

19. The method of claim 15, wherein controlling the security state of the integrated circuit device includes:

detecting a power signal being initially supplied to the at least one persistent region; and

in response to detecting the power signal being initially supplied to the at least one persistent region, changing the security state of the integrated device to the triggered security state.

20. The method of claim 15, wherein the master secret data includes data selected from the group consisting of a master key, a boot record, a file record, and combinations thereof.

21. A design structure embodied in a machine readable medium for designing or manufacturing an integrated circuit, the integrated circuit comprising:

a clock circuit being responsive to an external clock signal;

a security state machine configured to control a security state of the integrated circuit, wherein the security state machine is isolated from the clock circuit of the integrated circuit device; and

a master secret circuit in communication with the security state machine and configured to control access to master secret data, wherein the master secret circuit is isolated from the clock circuit of the integrated circuit device, and wherein the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data.

22. The design structure of claim 21, the integrated circuit further comprising:

at least one shadow register in communication with the master secret circuit and configured to capture at least a portion of the master secret data from, and communicate at least a portion of new master secret data to, the master secret circuit.

23. The design structure of claim 22, wherein the at least one shadow register is further configured to advance the security state of the integrated circuit.

24. The design structure of claim 21, the circuit further comprising:

a tamper event circuit in communication with the security state machine and configured to detect a tamper event of the integrated circuit, wherein the security state machine is responsive to the tamper event circuit to change the security state of the integrated circuit from a secured security state to a triggered security state in the event of the tamper event.