System and Method for Manufacturing Thick and Thin Film Devices Using a Donee Layer Cleaved From a Crystalline Donor

• US 20100133546A1
• Filed: 02/02/2010
• Published: 06/03/2010
• Est. Priority Date: 04/08/2005
• Status: Abandoned Application

• Current Assignee: Versatilis, LLC
• Original Assignee: Versatilis, LLC
• Inventors: Jain, Ajaykumar R.
• Application Number:
  US12/698,562
• Publication Number:
  US 20100133546A1
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01S 5/0207 Substrates having a special shape
• CPC Class Codes: Y10T 156/12 Surface bonding means and/or assembly means with cutting, punching, piercing, severing or tearing
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]

Abstract

Various embodiments of fabricated crystalline-based structures for the electronics, optoelectronics and optics industries are disclosed. Each of these structures is created in part by cleaving a donee layer from a crystalline donor, such as a micaceous/lamellar mass comprising a plurality of lamelliform sheets separable from each other along relatively weak cleavage planes. Once cleaved, one or more of these lamelliform sheets become the donee layer. The donee layer may be used for a variety of purposes, including a crystalline layer for supporting heteroepitaxial growth of one or more semiconductor layers thereon, an insulating layer, a barrier layer, a planarizing layer and a platform for creating useful structures, among others.

Claims

1. A system for manufacturing electronic and/or optoelectronic structures from at least one crystalline donor having a plurality of donee layers, each of the electronic and/or optoelectronic structures comprising a device layer containing at least one of 1) an electronic device and 2) an optoelectronic device, the system comprising:

an elongate handle;

a first roll for paying out the elongate handle;

at least one crystalline donor located downstream of said first roll, said at least one crystalline donor containing a plurality of donee layers;

a donee-layer affixer operatively located downstream of said first roll and operatively configured for affixing each of said plurality of donee layers to the elongate handle in succession with one another; and

a donee-layer cleaver operatively located relative to said donee-layer affixer and operatively configured to cleave each of the plurality of donee layers from said crystalline donor in succession with one another.

2. A system according to claim 1, further comprising at least one fabricator operatively configured for fabricating at least a portion of each said device layer on each of said plurality of donee layers.

3. A system according to claim 1, wherein said at least one crystalline donor comprises a micaceous/lamellar mass of lamelliform sheets.

4. A system according to claim 3, wherein said at least one crystalline donor comprises a plurality of fluorophlogopite sheets.

5. A system according to claim 3, further comprising a silicon deposition chamber located and configured for growing silicon on each of the plurality of donee layers.

6. A system according to claim 3, further comprising a germanium deposition chamber located and configured for growing germanium on each of the plurality of donee layers.

7. A system according to claim 3, further comprising a silicon-germanium deposition chamber located and configured for growing silicon germanium on each of the plurality of donee layers.

8. A system according to claim 3, further comprising a GaAs deposition chamber located and configured for growing GaAs on each of the plurality of donee layers.

9. A system according to claim 3, further comprising a GaP deposition chamber located and configured for growing GaP on each of the plurality of donee layers.

10. An electronic and/or optoelectronic device structure, comprising:

a first component layer comprising;

a first cleaved crystalline donee layer having a first cleaved surface and a second obverse cleaved surface spaced from said first cleaved surface; and

a first device layer, confronting said first cleaved surface, formed monolithically with said first cleaved crystalline donee layer, said first device layer containing at least one of

     1) an electronic device and

     2) an optoelectronic device.

11. An electronic and/or optoelectronic device structure according to claim 10, wherein said first cleaved crystalline donee layer comprises a lamelliform sheet from a micaceous/lamellar material.

12. An electronic and/or optoelectronic device structure according to claim 11, wherein said lamelliform sheet is a fluorophlogopite sheet from a unitary mass of micaceous/lamellar fluorophlogopite material.

13. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one transistor.

14. An electronic and/or optoelectronic device structure according to claim 13, wherein said at least one transistor is a thin-film transistor.

15. An electronic and/or optoelectronic device structure according to claim 13, wherein said at least one transistor is a thick-film transistor.

16. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one electroluminescent device.

17. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one energy sensor.

18. An electronic and/or optoelectronic device structure according to claim 10, further comprising a second component layer attached to said first component layer, said second component layer including:

a second cleaved crystalline donee layer having a second cleaved surface and a second obverse cleaved surface spaced from said second cleaved surface; and

a second device layer, confronting said second cleaved surface, formed monolithically with said second cleaved crystalline donee layer.

19. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one semiconductor-based transistor that includes silicon as the semiconductor.

20. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one semiconductor-based transistor that includes germanium as the semiconductor.

21. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one semiconductor-based transistor that includes silicon germanium as the semiconductor.

22. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one semiconductor-based transistor that includes GaAs as the semiconductor.

23. An electronic and/or optoelectronic device structure according to claim 10, wherein said first device layer comprises at least one semiconductor-based transistor that includes GaP as the semiconductor.

24. A method of making an electronic and/or optoelectronic device structure by layer transfer, comprising:

providing a crystalline donor having a first free surface and a plurality of intrinsic cleavage planes spaced from one another and each substantially parallel to the first surface, wherein the first free surface and a particular one of the plurality of intrinsic cleavage planes defining a first donee layer;

fabricating a device layer containing at least one device upon the first donee layer so that the at least one device is monolithic with the first donee layer, said at least one device being either one of an electronic type and an optoelectronic type;

securing a first handle to either the device layer or the first free surface of the first donee layer; and

cleaving the first donee layer from the crystalline donor along the particular one of the plurality of intrinsic cleavage planes so as to liberate the first donee layer, in combination with the first handle, from the crystalline donor;

wherein said fabricating of the device layer includes forming a single-crystal semiconductor layer on the first donee layer.

25. A method according to claim 24, wherein said fabricating of the device layer includes forming a single crystal layer of silicon on the first donee layer.

26. A method according to claim 24, wherein said fabricating of the device layer includes forming a single crystal layer of germanium on the first donee layer.

27. A method according to claim 24, wherein said fabricating of the device layer includes forming a single crystal layer of silicon germanium on the first donee layer.

28. A method according to claim 24, wherein said fabricating of the device layer includes forming a single crystal layer of GaAs on the first donee layer.

29. A method according to claim 24, wherein said fabricating of the device layer includes forming a single crystal layer of GaP on the first donee layer.