Low Latency Multi-Level Communication Interface

• US 20100134153A1
• Filed: 11/23/2009
• Published: 06/03/2010
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Zerbe, Jared L., Werner, Carl W., Chau, Pak S., Garlepp, Bruno W., Horowitz, Mark A., Garrett, Billy W. JR., Donnelly, Kevin S.
• Granted Patent: US 7,809,088 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

Claims

1. (canceled)

2. A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal, the multiphase receiver comprising:

a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock;

a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock; and

an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

3. The multiphase receiver of claim 2, wherein the equalization circuit is to adjust integration by applying a portion of an integration voltage generated by the first integrating receiver to an integration node of the second integrating receiver to precharge the integration node of the second integrating receiver.

4. The multiphase receiver of claim 3, wherein the equalization circuit is to adjust integration of a respective data bit by the second integrating receiver dependent on the result of integration of a previously received data bit by the first integrating receiver, wherein the respective data bit is the next data bit after the previously received data bit.

5. The multiphase receiver of claim 4, wherein the equalization circuit is to adjust integration by also applying a portion of an integration voltage generated by the second integrating receiver to an integration node of the first integrating receiver to precharge the integration node of the first integrating receiver.

6. The multiphase receiver of claim 4, the multiphase receiver being embodied as a double data rate receiver, the equalization circuit to apply an integration voltage for each data bit of an odd data cycle to precharge integration for an immediately subsequent data bit of an even data cycle, and to apply an integration voltage for each data value of an even data cycle to precharge integration for an immediately subsequent data bit of an odd data cycle.

7. The multiphase receiver of claim 6, wherein each of the first integrating receiver and the second integrating receiver also is to couple the respective integration voltage to a respective sense circuit to sense the logic state of a respective data bit.

8. The multiphase receiver of claim 2, wherein the first integrating receiver is to operate according to first edges of a timing reference signal and the second integrating receiver is to operate according to second edges of the timing reference signal that are complementary to the first edges.

9. The multiphase receiver of claim 2, wherein the equalization circuit comprises:

a first circuit to couple a result of integration by the first integrating receiver to the second integrating receiver to adjust integration by the second integrating receiver, and a second circuit to couple a result of integration by the second integrating receiver to a different integrating receiver to adjust integration by the different integrating receiver,

wherein each of the first and second circuits comprises a gain element and an adjustable element, the adjustable element to be controlled to vary an amount of equalization.

10. The multiphase receiver of claim 9, wherein:

the gain element of the first circuit comprises an operational amplifier to receive input based on the result of integration by the first integrating receiver;

the gain element of the second circuit comprises an operational amplifier to receive input based on the result of integration by the second integrating receiver;

the adjustable element of the first circuit comprises a transistor to couple an output of the operational amplifier of the first circuit with an integration node of the second integrating receiver to precharge the integration node of the second integrating receiver; and

the adjustable element of the second circuit comprises a transistor to couple an output of the operational amplifier of the second circuit with an integration node of the first integrating receiver to precharge the integration node of the first integrating receiver,

wherein the transistors of the adjustable elements each comprise a gate to be controlled to vary the amount of equalization.

11. The multiphase receiver of claim 10, wherein:

each of the first and second integrating receivers comprises a differential receiver comprising first and second integration nodes; and

the equalization circuit comprises at least four respective circuits, including the first and second circuits, to provide respective varying voltage offsets to respective integration nodes.

12. The multiphase receiver of claim 9, wherein the different integrating receiver is the first integrating receiver.

13. The multiphase receiver of claim 9, further comprising an equalization ratio control circuit to control the adjustable element.

14. The multiphase receiver of claim 13, wherein the equalization ratio control circuit comprises a digital-to-analog converter to generate an equalization control voltage to control the amount of equalization.

15. The multiphase receiver of claim 9, further comprising a programmable element to store a digital value representing the amount of equalization.

16. The multiphase receiver of claim 9, wherein the equalization circuit comprises an error compensation circuit to compensate for voltage offset error associated with one of the first and second integrating receivers.

17. The multiphase receiver of claim 2, further comprising:

timing adjustment circuitry to adjust integration by the first and second integrating receivers to compensate for data skew relative to a timing reference signal.

18. The multiphase receiver of claim 2, wherein integration by each of the respective first and second integrating receivers is responsive to a respective first timing reference signal, representing an end of a precharge period, and a respective second timing reference signal, representing a hold period.

19. The multiphase receiver of claim 2, wherein:

the integrating receiver distinct from the first integrating receiver comprises the second integrating receiver; and

the integrating receiver distinct from the second integrating receiver comprises the first integrating receiver.

20. The multiphase receiver of claim 2, wherein:

the integrating receiver distinct from the first integrating receiver consists of the second integrating receiver; and

the integrating receiver distinct from the second integrating receiver consists of the first integrating receiver.

21. The multiphase receiver of claim 2, embodied in a memory system.

22. The multiphase receiver of claim 2, embodied as a differential receiver.

23. A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal, the multiphase receiver comprising:

first means for integrating and sampling data of the input signal on a first phase of a clock;

second means for integrating and sampling data of the input signal on a second phase of the clock; and

means for correcting for intersymbol interference by applying portions of respective integration voltages generated by each of the first and second means to the other of the first and second means.

24. A method of compensating for intersymbol interference in the sampling of an input signal, the method comprising:

integrating and sampling data of the input signal on a first phase of a clock using a first integrating receiver;

integrating and sampling data of the input signal on a second phase of the clock using a second integrating receiver, wherein integration by the second integrating receiver is adjusted responsive to a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver; and

wherein integration by the first integrating receiver is adjusted responsive to a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver.

25. The method of claim 24, wherein the integrating receiver distinct from the first integrating receiver is the second integrating receiver, the input signal representing a double data rate signal.