TRI-STATE DELAY-TYPED PHASE LOCK LOOP

• US 20100134156A1
• Filed: 05/15/2009
• Published: 06/03/2010
• Est. Priority Date: 12/03/2008
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: HUANG, YI-SHUO, CHEN, PO-YEN, PAN, CHING-TSA, LIN, PAO-CHUAN
• Granted Patent: US 7,825,709 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

The present invention relates to a tri-state delay-typed phase lock loop, which comprises: a phase and frequency detector, a mode detector, a mode selector, a first sampling delay unit, a plurality of counters, a second sampling delay unit, and a phase and frequency calculator. The phase and frequency of the input reference signal can be determined automatically by the phase lock loop, and the output synchronization signal can be generated such that the frequency and the phase of the output synchronization signal are identical to those of the input reference signal.

Claims

1. A tri-state delay-typed phase lock loop, comprising:

a phase and frequency detector, for receiving an input reference signal, an output synchronous feedback signal, and a system sampling signal so as to obtain a first sampling value and a second sampling value according to said input reference signal, said output synchronous feedback signal and system sampling signal;

a mode detector, coupled to said phase and frequency detector, for receiving said first sampling value, said second sampling value, a previously sampling operating mode signal and said system sampling signal so as to obtain a positive edge tracking and recording counter value, a negative edge tracking and recording counter value, and a present sampling operating mode signal;

a first sampling delay unit, coupled to said mode detector, for receiving said present sampling operating mode signal so as to obtain the previously sampling operating mode signal;

a mode selector, coupled to said mode detector, for receiving said positive edge tracking and recording counter value, said negative edge tracking and recording counter value, and said present sampling operating mode signal so as to obtain a present operating mode record value;

a plurality of counters, respectively coupled to said mode detector and said mode selector, for receiving said present operating mode record value, said present sampling operating mode signal and said system sampling signal so as to obtain an output synchronous signal;

a second sampling delay unit, coupled to said counters, for receiving said output synchronous signal so as to obtain said output synchronous feedback signal; and

a phase and frequency calculator, coupled to said mode detector, for receiving said positive edge tracking and recording counter value, said negative edge tracking and recording counter value and said present sampling operating mode signal so as to obtain an angular frequency signal and a phase signal.

2. The tri-state delay-typed phase lock loop of claim 1, wherein the mode referred in said mode selector comprises a positive edge tracking amending state, a positive edge ahead tracking state, a positive edge lagging tracking state, a positive edge initial state, a positive edge ending state, a negative edge tracking amending state, a negative edge ahead tracking state, a negative edge lagging tracking state, a negative edge initial state and a negative edge ending state.

3. The tri-state delay-typed phase lock loop of claim 2, wherein if the mode is set to be said positive edge ahead tracking state, said a plurality of counters are decreased by 1 for their values.

4. The tri-state delay-typed phase lock loop of claim 2, wherein if the mode is set to be said positive edge lagging tracking state, said a plurality of counters are increased by 1 for their values.

5. The tri-state delay-typed phase lock loop of claim 2, wherein if the mode is set to be said negative edge ahead tracking state, said a plurality of counters are decreased by 1 for their values.

6. The tri-state delay-typed phase lock loop of claim 2, wherein if the mode is set to be said negative edge lagging tracking state, said a plurality of counters are increased by 1 for their values.

7. The tri-state delay-typed phase lock loop of claims 3, 4, 5, and 6, wherein the values of said a plurality of counters are varied by fuzzy control, polynomial function, or exponential function.

8. The tri-state delay-typed phase lock loop of claim 1, wherein if one of said a plurality of counters stops counting, logic 1 is outputted.

9. The tri-state delay-typed phase lock loop of claim 1, wherein if another one of said a plurality of counters stops counting, logic 0 is outputted.