CLOCK EXTRACTION DEVICE WITH DIGITAL PHASE LOCK, REQUIRING NO EXTERNAL CONTROL
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Abstract
A device for extracting a clock signal from a baseband serial signal, includes an injection-locked oscillator (19), a phase-locked loop (25) including a digital phase detector (26). The oscillator (19) includes a digital input for controlling the value of its natural frequency, and the phase-locked loop (25) includes a counting circuit (30, 35) aggregating the relative values of the digital signal supplied by the digital phase detector (26) and supplying a control signal in digital form for the oscillator (19).
33 Citations
37 Claims
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1-18. -18. (canceled)
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19. Device for clock extraction from a baseband serial signal, known as the received signal, that is representative of digital data and coded with a clock signal exhibiting a clock-bit frequency fsr, including:
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a circuit receiving a signal resulting from the received signal and clocked at the clock-bit frequency fsr and supplying, to at least one clock output, a clock signal, known as the reception clock signal, at least substantially synchronised and in phase with the clock-bit frequency fsr of the received signal, a phase-control loop including; a first input connected to a clock output of the circuit supplying a reception clock signal, a second input which is fed by a signal resulting from the received signal, a digital phase detector including a lead/lag detector connected to the first and second inputs and adapted to supply to at least one output at least one digital signal, known as the phase-state signal, that is representative of a phase shift between the reception clock signal and the received signal, and of the direction of this shift, an output supplying a signal, known as the control signal, connected to an input, known as the command input, of the circuit supplying a reception clock signal, which is adapted so that the value of the frequency of the reception clock signal depends on the value of the control signal received at this control input, a circuit, known as the counting circuit, exhibiting an input connected to said output of the digital phase detector, said counting circuit being adapted to implement at least one filtering by digital counting/down-counting in respect of the variations of the relative values of the digital signal which are supplied in time by the phase detector, and to supply a control signal in digital form, the value of which is a function of the result of this/these filtering(s), this value of the control signal being adapted to set a value of the frequency of the reception clock signal equal to a value, filtered in this way, of the clock-bit frequency fsr of the reception clock signal, wherein; the circuit supplying a reception clock signal is an injection-locked oscillator with digital control, including a digital control input which is adapted to be able to receive the control signal supplied by the phase-control loop in digital form, and so that the value of the natural frequency fos of the oscillator depends on the value of the control signal received at this control input, the phase-control loop includes a circuit exhibiting at least one input connected respectively to the output(s) of the lead/lag detector and supplying to at least one output a digital signal, known as the filtered phase-state signal; having a first relative value after reception of a predetermined number N greater than 1 of successive identical values at the input, corresponding to N successive data bits of the received signal for which the lead/lag detector has detected a phase shift in the same direction, having a second relative value after reception of N successive identical values at the input, corresponding to N successive data bits of the received signal for which the lead/lag detector has detected a phase shift in the other direction, having a third relative value in the other cases, so that the relative value of the filtered phase-state signal is representative of the presence of a phase shift in the same direction and of the direction of this phase shift, for N successive data bits of the received signal, between the edges of the reception clock signal and the corresponding data bits of the received signal. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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Specification