Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors

• US 20100134182A1
• Filed: 02/08/2010
• Published: 06/03/2010
• Est. Priority Date: 07/07/2004
• Status: Active Grant

• Current Assignee: Ashok Kumar Kapoor, Reuven Marko, Robert Strain
• Original Assignee: Ashok Kumar Kapoor, Reuven Marko, Robert Strain
• Inventors: Marko, Reuven, Strain, Robert, KAPOOR, Ashok Kumar
• Granted Patent: US 8,048,732 B2
• Time in Patent Office: Days
• US Class Current: 327/541
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Claims

1. A method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor having a source terminal, a drain terminal, a gate terminal, and a well terminal, said method comprising the steps of:

forming a first MOS transistor over a well;

forming, at least one forward biased diode between said gate and said well of said first MOS transistor; and

forming a capacitor in parallel with said at least one forward biased diode.

2. The method of claim 1, further comprising the step of:

forming a resistor in series with said diode.

3. The claim of claim 1, further comprising the step of:

forming a resistor in series with said capacitor.

4. The method of claim 1, said first MOS transistor comprising any of:

an n-channel device; and

a p-channel device.

5. The method of claim 4, further comprising the step of:

if said first MOS transistor is an n-channel device, forming a second MOS transistor comprising an n-channel device having a drain that is coupled to said first MOS transistor drain.

6. The method of claim 4, further comprising the step of:

if said first MOS transistor is an n-channel device, forming a biasing circuit for providing a positive bias to the well of said first MOS transistor.

7. The method of claim 4, further comprising the step of:

if said first MOS transistor is an p-channel device, forming a biasing circuit for providing a negative bias to the well of said first MOS transistor.

8. The method of claim 1, said step of forming a diode comprising the step of:

forming any of a diffused diode, a self-aligned diode, an in-line polysilicon diode, and a Schottky diode.

9. The method of claim 8, wherein, if said diode comprises a polysilicon diode, said step of forming said diode comprising the steps of:

forming a uniform implant; and

forming an opposite heavy implant.

10. The method of claim 1, further comprising the step of:

doping the well of said MOS transistor to a level optimized for reduction of said leakage current.

11. A method for reducing leakage current and increasing drive current in a metal-oxide-semiconductor (MOS) transistor having a source terminal, a drain terminal, a gate terminal, and a well terminal, said method comprising the steps of:

connecting a control circuit between said gate terminal and said well terminal of said MOS transistor, the control circuit comprised of at least a forward biased diode and at least a capacitor connected in parallel with said diode;

operating said control circuit to cause said MOS transistor to have a high threshold voltage in a transistor OFF state;

operating said control circuit to cause said MOS transistor to have a low threshold voltage in a transistor ON state; and

operating said control circuit to control a waveform at said well terminal of said MOS transistor.

12. The method of claim 11, further comprising the step of:

providing a positive bias to the well of said MOS transistor if said MOS transistor comprises an n-channel device in the on state, to cause a decrease in the magnitude of threshold voltage; and

providing a negative bias to the well of said MOS transistor if said MOS transistor is a p-channel device in the on state, to cause a decrease in the magnitude of the threshold voltage.

13. A method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor having a source terminal, a drain terminal, a gate terminal, and a well terminal, said method comprising the steps of:

forming a first circuit element comprising at least one forward biased diode connected between said gate and said well of said MOS transistor; and

forming a second circuit comprising a capacitor parallel with said first circuit element;

wherein said MOS transistor comprises any of an n-channel device and a p-channel device.

14. The method of claim 13, further comprising the step of:

if said MOS transistor comprises an n-channel device, forming means for providing a bias to the source of the MOS transistor that is positive relative to the well of said MOS transistor.

15. The method of claim 13, further comprising the step of:

if said MOS transistor comprises a p-channel device, forming means for providing a bias to the source of the MOS transistor that is negative relative to the well of said MOS transistor.

16. The method of claim 13, further comprising the step of:

forming said first circuit element comprising a resistor in series with said diode.

17. The method of claim 13, further comprising the step of:

forming said second circuit element comprising a resistor in series with said capacitor.

18. The method of claim 13, said step of forming a first circuit element comprising the steps of:

forming at least one diffused diode by diffusing n-type and p-type layers in an isolated structure; and

adjusting doping profiles in silicon and programming diode area to control a forward voltage drop across said diode.

19. The method of claim 18, further comprising the step of:

using a deep n-type implant to form NMOS transistors in a p-type well that is isolated from a p-type substrate.

20. The method of claim 13, said step of forming a second circuit further comprising the step of:

forming a metal-on-metal (MoM) capacitor using fringing capacitance between interdigitated metal fingers.