SWITCH AND METHOD OF FORMING THE SAME

• US 20100135064A1
• Filed: 07/31/2009
• Published: 06/03/2010
• Est. Priority Date: 12/02/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Jun, Jang, Weon-Wi, Kwon, Yong-Hyun, Cho, Keun-Hwi, Kim, Dong-Won, Kim, Min-Sang, Bae, Hyun-Jun, Lee, Ji-Myoung
• Granted Patent: US 8,391,057 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/685 Hi-Lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.

Claims

1. A memory device comprising:

a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node is configured to store an electrical charge, and the first electrode is movable to connect to the storage node when the second electrode is energized.

2. The memory device of claim 1, wherein the first electrode comprises a vertical portion, a first horizontal portion, and a second horizontal portion, the vertical portion is substantially perpendicular with respect to the major horizontal plane of a substrate on which the memory cell is disposed and the first and second horizontal portions are substantially parallel with respect to the major horizontal plane of the substrate.

3. The memory device of claim 2, wherein a first end of the vertical portion is connected to a first end of the first horizontal portion, a second end of the first horizontal portion is fixed to an insulator pattern formed over the second electrode, a second end of the vertical portion is connected to a first end of the second horizontal portion.

4. The memory device of claim 3, wherein a gap is formed between the vertical portion of the first electrode and the storage node and the second electrode.

5. The memory device of claim 4, wherein the second end of the vertical portion is separated from the storage node by the gap when the second electrode is not energized.

6. The memory device of claim 5, wherein the second end of the vertical portion contacts the storage node when the second electrode is energized.

7. The memory device of claim 3, wherein the second end of the vertical portion is protruded toward the storage node.

8. The memory device of claim 1, wherein the second electrode is energized when a voltage is applied.

9. The memory device of claim 1, wherein the storage node comprises a capacitor, the first electrode comprises a bit line, and the second electrode comprises a word line.

10. A memory device comprising:

a memory cell that includes a first electrode, a second electrode, and a storage node, the first electrode is separated from the second electrode with a first gap and is separated from the storage node with a second gap, and the first electrode moves to connect to the storage node when the second electrode is energized.

11. The memory device of claim 10, wherein the first gap and the second gap are substantially the same.

12. The memory device of claim 10, wherein the first gap is larger than the second gap.

13. A memory device comprising:

a first memory cell including a first word line, a first capacitor, and a first bit line;

a second memory cell including a second word line, a second capacitor, and a second bit line connected to the first bit line;

wherein the first bit line is movable to connect to the first capacitor when the first word line is energized and the second bit line is movable to connect to the second capacitor when the second word line is energized.

14. The memory device of claim 13, wherein the first bit line in the first memory cell comprises a first vertical portion, the second bit line in the second memory cell comprises a second vertical portion, the first and second vertical portions are substantially perpendicular with respect to the major horizontal plane of a substrate on which the first and second memory cells are disposed and substantially parallel with respect to each other.

15. The memory device of claim 14, wherein an end of the first vertical portion is separated from the first capacitor when the first word line is not energized, and the end of the first vertical portion contacts the first capacitor when the first word line is energized.

16. The memory device of claim 15, wherein the end of the first vertical portion is protruded toward the first capacitor.

17. The memory device of claim 14, wherein an end of the second vertical portion is separated from the second capacitor when the second word line is not energized, and the end of the second vertical portion contacts the second capacitor when the second word line is energized.

18. The memory device of claim 17, wherein the end of the second vertical portion is protruded toward the second capacitor.

19. The memory device of claim 13, wherein the first word line and the second word line are energized when a voltage is applied.

20. The memory device of claim 13, wherein an insulator pattern is formed over the first word line and the second word line, and the first and second bit lines are fixed to the insulator pattern.

21. The memory device of claim 20, wherein the first and second bit lines are substantially symmetrical with respect to the insulator pattern.

22. A memory device comprising:

a substrate;

a capacitor formed on the substrate, the capacitor stores an electrical charge;

a word line disposed over the capacitor; and

a bit line fixed to an insulator pattern formed over the word line, the bit line is separated from the word line and the capacitor with a gap, the bit line having a vertical portion substantially perpendicular with respect to the major horizontal plane of the substrate,

wherein the vertical portion of the bit line is movable to connect to the capacitor when the word line is energized.

23. The memory device of claim 22, further comprising a first interlayer dielectric layer formed between the word line and the capacitor.

24. The memory device of claim 23, further comprising a second interlayer dielectric layer formed between the word line and the insulator pattern.

25. The memory device of claim 22, wherein the bit line further comprises a parallel portion, a first end of the parallel portion is connected to a first end of the vertical portion and a second end of the parallel portion is fixed to the insulator pattern.

26. The memory device of claim 25, wherein a second end of the vertical portion of the bit line is separated from the capacitor when the word line is not energized.

27. The memory device of claim 26, wherein a second of the vertical portion of the bit line contacts the capacitor when the word line is energized.

28. The memory device of claim 27, wherein the second end of the vertical portion is protruded toward the capacitor.

29. The memory device of claim 22, wherein the word line is energized when a voltage is applied.

30. The memory device of claim 22, wherein the bit line comprises at least two layers.