METHOD OF OPERATING NON-VOLATILE MEMORY CELL AND MEMORY DEVICE UTILIZING THE METHOD

• US 20100135086A1
• Filed: 12/02/2008
• Published: 06/03/2010
• Est. Priority Date: 12/02/2008
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Wu, Chao-I
• Granted Patent: US 7,986,558 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method of operating a non-volatile memory cell is described, including pre-erasing the cell through double-side biased (DSB) injection of a first type of carrier and programming the cell through Fowler-Nordheim (FN) tunneling of a second type of carrier.

Claims

1. A method of operating a non-volatile memory cell, comprising:

pre-erasing the cell through double-side biased (DSB) injection of a first type of carrier; and

programming the cell through Fowler-Nordheim (FN) tunneling of a second type of carrier.

2. The method of claim 1, wherein the DSB injection comprises DSB band-to-band tunneling hot carrier injection.

3. The method of claim 1, wherein the FN tunneling comprises positive FN (+FN) tunneling.

4. The method of claim 1, wherein the first type of carrier is electric hole and the second type of carrier is electron.

5. The method of claim 1, wherein

the cell comprises a semiconductor layer, a charge storage layer and a control gate over the semiconductor layer, and a source and a drain in the semiconductor layer;

and

in pre-erasing the cell, a first voltage is applied to the control gate and a second voltage to the source and the drain, wherein the first voltage is different from the second voltage such that DSB injection of the first type of carrier into the charge storage layer is caused.

6. The method of claim 5, wherein the first voltage is lower than 0V and the second voltage is higher than 0V.

7. The method of claim 6, wherein the first voltage ranges from −

10 V to −

20 V and the second voltage ranges from 8 V to 12V.

8. The method of claim 1, wherein

the cell comprises a semiconductor layer, a charge storage layer and a control gate over the semiconductor layer, and a source and a drain in the semiconductor layer;

and

in programming the cell, a first voltage is applied to the control gate and a second voltage to the source and the drain, wherein the first voltage is different from the second voltage such that FN tunneling of the second type of carrier into the charge storage layer is caused.

9. The method of claim 8, wherein the first voltage is higher than 0V and the second voltage is 0V.

10. The method of claim 9, wherein the first voltage ranges from 15 V to 20 V.

11. The method of claim 1, wherein the memory cell comprise a semiconductor layer, a charge storage layer and a control gate over the semiconductor layer, and a source and a drain in the semiconductor layer, wherein the semiconductor layer is a floating body disposed on an insulator.

12. The method of claim 11, wherein the memory cell is a thin-film transistor (TFT), the semiconductor layer and the control gate both comprise doped silicon, and the charge storage layer comprises a nitride layer between two oxide layers, so that the memory cell is a TFT SONOS cell.

13. A memory device, comprising:

a memory cell;

a first logic for pre-erasing the memory cell through double-side biased (DSB) injection of a first type of carrier; and

a second logic for programming the memory cell through Fowler-Nordheim (FN) tunneling of a second type of carrier.

14. The memory device of claim 13, wherein the first type of carrier is electric hole and the second type of carrier is electron.

15. The memory device of claim 13, wherein the DSB injection comprises DSB band-to-band tunneling hot carrier injection.

16. The memory device of claim 13, wherein the FN tunneling comprises positive FN (+FN) tunneling.

17. The memory device of claim 13, wherein the first type of carrier is electric hole, the second type of carrier is electron, the DSB injection comprises DSB band-to-band tunneling hot hole injection, and the FN tunneling comprises positive FN (+FN) tunneling of electrons.