Low power, high resolution timing generator for ultra-wide bandwidth communication systems

• US 20100135358A1
• Filed: 11/24/2009
• Published: 06/03/2010
• Est. Priority Date: 05/26/2000
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: McCorkle, John W.
• Granted Patent: US 7,903,778 B2
• Time in Patent Office: Days
• US Class Current: 375/130
• CPC Class Codes: G01S 13/0209 Systems with very large relative bandwidth, i.e. larger than 10 %, e.g. baseband, pulse, carrier-free, ultrawideband
• CPC Class Codes: G01S 7/023 Interference mitigation, e.g. reducing or avoiding non-intentional interference with other HF-transmitters, base station transmitters for mobile communication or other radar systems, e.g. using electro-magnetic interference [EMI] reduction techniques auxiliary means for detecting or identifying radar signals or the like G01S7/021; means for anti-jamming G01S7/36
• CPC Class Codes: G01S 7/0232 Avoidance by frequency multiplex
• CPC Class Codes: H04B 1/71635 Transmitter aspects H04B1/7174 takes precedence
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 1/7172 Pulse shape in general H04L25/03834
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 27/0004 using wavelets

Abstract

A control generator is provided, comprising: a summer configured to add a ramping phase adjustment signal and a basic phase adjustment signal to generate a combined phase adjustment signal based on the combined phase adjustment signal; a look-up table configured to generate first through N^th digital phase and frequency adjustment signals; and first through N^th digital to analog converters configured to convert the first through N^th digital phase and frequency adjustment signals to first through N^th analog phase and frequency adjustment signals in accordance with first through N^th clock signals, respectively. wherein N is an integer greater than 1.

Claims

1. A control generator, comprising:

a summer configured to add a ramping phase adjustment signal and a basic phase adjustment signal to generate a combined phase adjustment signal based on the combined phase adjustment signal;

a look-up table configured to generate first through N^th digital phase and frequency adjustment signals; and

first through N^th digital to analog converters configured to convert the first through N^th digital phase and frequency adjustment signals to first through N^th analog phase and frequency adjustment signals in accordance with first through N^th clock signals, respectively,

wherein N is an integer greater than 1.

2. The control generator of claim 1, further comprising first through N^th low pass filters configured to filter the first through N^th analog phase and frequency adjustment signals to generate first through N^th filtered phase and frequency adjustment signals.

3. The control generator of claim 1, wherein the first through N^th analog phase and frequency adjustment signals are sinusoidal signals.

4. The control generator of claim 1, further comprising a clock generation circuit configured to generate the first through N^th clock signals.

5. The control generator of claim 4,

wherein the clock generation circuit is a quadrature network configured to generate the first clock signal and a second clock signal, and

wherein the second clock signal is a 90°

phase-shifted version of the first clock signal.

6. The control generator of claim 1,

wherein N is 2, and

wherein a second clock signal is a 90°

phase-shifted version of the first clock signal.

7. The control generator of claim 1,

wherein N is 3, and

wherein the first through third clock signals are the same.

8. A control generator, comprising:

a clock generation circuit configured to generate the first through M^th clock signals;

a summer configured to add a ramping phase adjustment signal and a basic phase adjustment signal to generate a combined phase adjustment signal;

a look-up table configured to generate first through N^th digital phase and frequency adjustment signals based on the combined phase adjustment signal;

a multiplexer configured to select one of the first through N^th digital phase and frequency adjustment signals based on a control signal;

a digital to analog converter configured to convert the selected digital phase and frequency adjustment signal to a selected analog phase and frequency adjustment signal in accordance with first through N^th clock signals, respectively; and

first through N^th primary sample and hold circuits, each configured to perform a sample and hold operation on the selected analog phase and frequency adjustment signal based on one or more of the first through M^th clock signals, to generate a corresponding first through N^th primary sampled phase and frequency adjustment signals,

wherein the control signal is generated based on the first through M^th clock signals, and

wherein N is an integer greater than 1.

9. The control generator of claim 8, further comprising first through N^th low pass filters configured to filter the first through N^th sampled phase and frequency adjustment signals to generate first through N^th filtered phase and frequency adjustment signals.

10. The control generator of claim 8, wherein the first through N^th analog phase and frequency adjustment signals are sinusoidal signals.

11. The control generator of claim 8, further comprising a clock generation circuit configured to generate the first through M^th clock signals.

12. The control generator of claim 11,

wherein M is 2,

wherein the clock generation circuit is a quadrature network configured to generate the first clock signal and a second clock signal, and

wherein the second clock signal is a 90°

phase-shifted version of the first clock signal.

13. The control generator of claim 11,

wherein M is 4,

wherein the clock generation circuit is a phasing network configured to generate the first through fourth clock signals,

wherein a second clock signal is a 90°

phase-shifted version of the first clock signal,

wherein a third clock signal is a 180°

phase-shifted version of the first clock signal, and

wherein a fourth clock signal is a 270°

phase-shifted version of the first clock signal.

14. The control generator of claim 8,

wherein N and M are both 2,

wherein a second clock signal is a 90°

phase-shifted version of the first clock signal,

wherein the first primary sample and hold circuit operates in response to the first clock signal,

wherein the second primary sample and hold circuit operates in response to the second clock signal, and

wherein the first digital phase and frequency adjustment signal and the second digital phase and frequency adjustment signal are 90°

out of phase from each other.

15. The control generator of claim 8,

wherein N is 3 and M is 4,

wherein a second clock signal is a 90°

phase-shifted version of the fist clock signal,

wherein a third clock signal is a 180°

phase-shifted version of the first clock signal,

wherein a fourth clock signal is a 270°

phase-shifted version of the first clock signal,

wherein the first primary sample and hold circuit operates in response to the first clock signal,

wherein the second primary sample and hold circuit operates in response to the second clock signal, and

wherein the third primary sample and hold circuit operates in response to the third clock signal.

16. The control generator of claim 15,

further comprising first through N^th secondary sample and hold circuits, each configured to perform a sample and hold operation on corresponding first through N^th primary sampled phase and frequency adjustment signals to generate a corresponding first through N^th secondary sampled phase and frequency adjustment signals,

wherein the secondary sample and hold circuits each operate in response to the fourth clock signal.