METHODS FOR FORMING BIT LINE CONTACTS AND BIT LINES DURING THE FORMATION OF A SEMICONDUCTOR DEVICE
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Abstract
A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.
22 Citations
31 Claims
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1-16. -16. (canceled)
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17. A method for use during fabrication of a semiconductor device, comprising:
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forming a plurality of conductive bit line plugs at a first cross-sectional location and at a second cross-sectional location; forming a first blanket conductive bit line layer which contacts the plurality of conductive bit line plugs at the first and second cross-sectional locations; and removing a portion of the first blanket conductive bit line layer to form a plurality of first bit lines which contact the bit line plugs at the first location, but which is removed from contact with the bit line plugs at the second location. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A method for use during fabrication of a semiconductor device, comprising:
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providing a semiconductor wafer substrate assembly comprising a plurality of conductive regions; providing a plurality of conductive plugs within a first dielectric layer at a first cross-sectional location and at a second cross-sectional location, wherein each conductive plug electrically contacts one of the conductive regions; forming a first blanket conductive layer to electrically contact each of the conductive plugs at both the first cross-sectional location and the second cross-sectional location; forming a blanket second dielectric layer over the blanket conductive layer; etching the blanket second dielectric layer and the blanket conductive layer to form a plurality of first conductive lines from the first blanket conductive layer, wherein subsequent to the etch a conductive line contacts each of the conductive plugs at the first cross-sectional location, but no portion of the first blanket conductive layer contacts any of the conductive plugs at the second cross-sectional location; providing a mask layer interposed between adjacent first conductive lines at the first cross-sectional location, wherein the mask layer leaves the conductive plugs at the second cross-sectional location exposed; forming a second blanket conductive layer over the mask layer at the first cross-sectional location which contacts the conductive plugs at the second cross-sectional location; planarizing the second blanket conductive layer to remove the second blanket conductive layer from over the mask layer at the first cross-sectional location and to leave the second conductive layer contacting the conductive plugs at the second cross-sectional location; and forming a plurality of second conductive lines to contact the second conductive layer at the second cross-sectional location, wherein a bottom surface of the second conductive lines at the first cross sectional location is above a top surface of the first conductive lines. - View Dependent Claims (24, 25, 26, 27)
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28. A method for use during fabrication of a semiconductor device, comprising:
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forming a plurality of conductive bit line plugs at a first cross-sectional location and at a second cross-sectional location; forming a first blanket conductive bit line layer which contacts the plurality of conductive bit line plugs at the first and second cross-sectional locations; and removing a portion of the first blanket conductive bit line layer to form a plurality of first bit lines which contact the bit line plugs at the first location, but which is removed from contact with the bit line plugs at the second location; forming a dielectric layer over the plurality of first bit lines and bit line plugs at the first cross-sectional location, and over the first bit lines and bit line plugs at the second cross-sectional location; forming a patterned mask over the bit line plugs at the first cross-sectional location and over the first bit lines at both the first and second cross-sectional locations, wherein the bit line plugs at the second location is uncovered by the patterned mask; etching the dielectric layer using the patterned mask as a pattern to form a plurality of openings in the first dielectric layer which expose the bit line contacts at the second location; forming a second conductive bit line layer over both the dielectric layer and over the first bit line layer at the first and second cross-sectional locations, and within the plurality of openings in the first dielectric layer to contact the bit line plugs at the second cross-sectional location, wherein the second conductive bit line layer does not contact the bit line plugs at the first cross-sectional location; and etching the second conductive bit line layer at the first and second cross-sectional locations to form a plurality of second bit lines, wherein at least a portion of the second conductive bit line layer remains within the plurality of openings at the second cross-sectional location and over the dielectric layer at the first cross-sectional location subsequent to the etching of the second conductive bit line layer. - View Dependent Claims (29, 30)
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31-47. -47. (canceled)
Specification