Digital Signal Processor Having Instruction Set With One Or More Non-Linear Complex Functions

• US 20100138468A1
• Filed: 11/28/2008
• Published: 06/03/2010
• Est. Priority Date: 11/28/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Williams, Joseph, Chen, Jian-Guo, Azadet, Kameran, Hijazi, Samer
• Granted Patent: US 9,176,735 B2
• Time in Patent Office: Days
• US Class Current: 708/511
• CPC Class Codes: G06F 9/3001 Arithmetic instructions

Abstract

Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.

Claims

1. A method performed by a processor, comprising:

obtaining one or more non-linear complex software instructions having at least one complex number as an input;

applying one or more non-linear complex functions from a predefined instruction set to said at least one complex number; and

generating an output comprised of one complex number or two real numbers.

2. The method of claim 1, wherein at least one functional unit implements said one or more non-linear complex functions.

3. The method of claim 1, wherein said at least one complex input number comprises a complex vector comprised of a plurality of complex numbers and wherein said processor processes said plurality of complex numbers in parallel.

4. The method of claim 1, wherein said processor executes said software instructions from program code.

5. A processor, comprising:

an input for receiving one or more non-linear complex software instructions having at least one complex number as an input;

at least one functional unit for applying one or more non-linear complex functions from a predefined instruction set to said at least one complex number; and

an output for providing at least one complex number or two real numbers.

6. The processor of claim 5, wherein said at least one complex input number comprises a complex vector comprised of a plurality of complex numbers.

7. The processor of claim 6, wherein a plurality of said at least one functional units process said plurality of complex numbers in parallel.

8. The processor of claim 5, wherein said processor executes said software instructions from program code.

9. An integrated circuit, comprising:

a processor, comprising;

an input for receiving one or more non-linear complex software instructions having at least one complex number as an input;

at least one functional unit for applying one or more non-linear complex functions from a predefined instruction set to said at least one complex number; and

an output for providing at least one complex number or two real numbers.

10. The integrated circuit of claim 9, wherein said at least one complex input number comprises a complex vector comprised of a plurality of complex numbers.

11. The integrated circuit of claim 9, wherein a plurality of said at least one functional units process said plurality of complex numbers in parallel.

12. The integrated circuit of claim 9, wherein said processor executes said software instructions from program code.