MEMORY SYSTEM WITH DYNAMIC SUPPLY VOLTAGE SCALING

• US 20100138684A1
• Filed: 12/02/2008
• Published: 06/03/2010
• Est. Priority Date: 12/02/2008
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation, Chrysler LLC (Stellantis NV)
• Original Assignee: International Business Machines Corporation
• Inventors: Patel, Vipin, Gara, Alan, Coteus, Paul W., Wright, Kenneth L., Kim, Kyu-hyoun
• Application Number:
  US12/326,126
• Publication Number:
  US 20100138684A1
• Time in Patent Office: Days
• US Class Current: 713/601
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock.

Claims

1. A memory device comprising:

a memory core, the memory core responsive to a variable external supply voltage configurable by a memory controller between a lower power mode of operation and a higher power mode of operation.

2. The memory device of claim 1 wherein the memory device receives a clock with a configurable frequency from the memory controller comprising a lower clock frequency in the lower power mode of operation and a higher clock frequency in the higher power mode of operation.

3. The memory device of claim 1 wherein the memory device is a synchronous dynamic random access memory chip.

4. The memory device of claim 1 further comprising a memory input/output interface to interface bus signals from the memory controller to the memory core, wherein voltage supplied to the memory input/output interface is independently regulated with respect to the memory core.

5. The memory device of claim 4 wherein voltage supplied to the memory core is an internally regulated supply voltage derived from the variable external supply voltage.

6. The memory device of claim 5 wherein the memory device includes a regulator controlled by the memory controller, the regulator producing the internally regulated supply voltage.

7. The memory device of claim 6 wherein the memory core further comprises an array of storage cells and periphery circuitry to control access to the array, and further wherein the internally regulated supply voltage is provided to the array and the variable external supply voltage is provided to the periphery circuitry.

8. The memory device of claim 1 wherein the variable external supply voltage is supplied to multiple memory devices on a memory module arranged as one or more ranks with independent control of the variable external supply voltage per rank.

19. The method of claim 1, wherein the memory controller accesses a serial presence detect on a memory module to determine whether the memory module supports supply voltage scaling.

9. A memory controller comprising:

memory control logic to interface with a processor;

a memory input/output interface to interface with a memory device; and

supply voltage control logic to decrease supply voltage delivered from a power supply to the memory device in response to a request for a lower power mode of operation, and increasing the supply voltage delivered from the power supply to the memory device in response to a request for a higher power mode of operation.

10. The memory controller of claim 9 further comprising a memory clock generator to provide a clock to the memory device, wherein the memory clock generator provides a reduced clock frequency to the memory device in the lower power mode of operation and the higher clock frequency to the memory device in the higher power mode of operation.

11. The memory controller of claim 9 further comprising:

a memory parameter look-up table to configure memory parameters in response to the mode of operation, wherein the memory parameters include timing, clock frequency, and level of the supply voltage.

12. The memory controller of claim 11 wherein the memory controller supports additional modes of operation as defined in the memory parameter look-up table.

13. The memory controller of claim 11 further comprising a temperature interface to acquire a temperature, wherein the lower power mode of operation is requested in response the temperature exceeding a threshold, and the higher power mode of operation is requested in response the temperature being below the threshold.

14. The memory controller of claim 9 wherein the power supply adjusts the supply voltage external to the memory device.

15. The memory controller of claim 9 wherein mode of operation requests are generated from one of:

the processor and memory power management logic within the memory controller.

16. A method comprising:

receiving a request for a supply voltage change at a memory controller in a memory system, the supply voltage powering a memory device;

waiting for any current access of the memory device to complete;

disabling a clock between the memory controller and the memory device;

changing the supply voltage responsive to the request; and

enabling the clock.

17. The method of claim 16 further comprising:

adjusting a clock frequency of the clock prior to enabling the clock.

18. The method of claim 17 wherein the memory controller includes a memory parameter look-up table, the supply voltage change is associated with an operating mode defined in the memory parameter look-up table, and the memory controller further adjusts a timing parameter for accessing the memory device in response to a timing value in the memory parameter look-up table associated with the operating mode.

20. The method of claim 16 wherein the supply voltage is adjusted external to the memory device in response to a control command from the memory controller.

21. A design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

memory control logic to interface with a processor;

a memory input/output interface to interface with a memory device; and

supply voltage control logic to decrease supply voltage delivered from a power supply to the memory device in response to a request for a lower power mode of operation, and increasing the supply voltage delivered from the power supply to the memory device in response to a request for a higher power mode of operation.

22. The design structure of claim 21, wherein the design structure comprises a netlist.

23. The design structure of claim 21, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

24. The design structure of claim 21, wherein the design structure resides in a programmable gate array.