DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS

• US 20100138708A1
• Filed: 12/17/2009
• Published: 06/03/2010
• Est. Priority Date: 07/21/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mrugalski, Grzegorz, Tyszer, Jerzy, Rajski, Janusz, Czysz, Dariusz
• Granted Patent: US 8,015,461 B2
• Time in Patent Office: Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Claims

1-15. -15. (canceled)

16. A method, comprising:

inputting compressed test pattern bits;

generating decompressed test pattern bits from the compressed test pattern bits;

storing the decompressed test pattern bits in one or more registers; and

loading scan chains of a circuit-under-test with the decompressed test pattern bits stored in the one or more registers, the loading being performed for two or more scan chain shift cycles such that the decompressed test pattern bits stored in the one or more registers are repeatedly loaded into the scan chain.

17. The method of claim 16, wherein the compressed test pattern bits are a first set of compressed test pattern bits, wherein the decompressed test pattern bits are a first set of decompressed test pattern bits, and wherein the method further comprises:

inputting a second set of compressed test pattern bits;

generating a second set of decompressed test pattern bits from the second set of compressed test pattern bits; and

storing the second set of decompressed test pattern bits in the one or more registers, thereby replacing the first set of decompressed test pattern bits in the one or more registers.

18. The method of claim 17, wherein the two or more scan chain shift cycles comprises a first set of two or more scan chain shift cycles, the method further comprising loading the scan chains of the circuit-under-test with the second set of decompressed test pattern bits stored in the one or more registers, the loading being performed for a second set of two or more scan chain shift cycles such that the second set of decompressed test pattern bits are repeatedly loaded into the scan chain.

19. The method of claim 16, wherein the two or more scan chain shift cycles are consecutive scan chain shift cycles.

20. The method of claim 16, wherein the one or more registers comprise at least one shadow register.

21. The method of claim 16, the method further comprising outputting the compressed test pattern bits from a tester external to the circuit-under-test.

22. The method of claim 16 performed in a simulation environment.

23. One or more computer-readable media comprising computer-executable instructions for causing a computer to simulate the method of claim 16.

24. An apparatus, comprising:

a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs;

a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs; and

a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs.

25. The apparatus of claim 24, further comprising a control channel coupled to a clock input of the register.

26. The apparatus of claim 25, wherein the control channel is coupled to the clock input of the shadow register via a logic gate.

27. The apparatus of claim 26, wherein the logic gate is an AND gate.

28. The apparatus of claim 25, wherein the control channel receives input from a single pin of the circuit-under-test.

29. The apparatus of claim 25, wherein the control channel is coupled to one or more logic gates, the logic gates being coupled to one or more test data inputs of the circuit-under-test.

30. The apparatus of claim 24, wherein the logic gates form an XOR network.

31. The apparatus of claim 24, wherein the LFSM is a linear feedback shift register (LFSR).

32. The apparatus of claim 24, wherein the LFSM is a ring generator.

33. The apparatus of claim 24, wherein the register is a first register, the apparatus further comprising a second register comprising two or more second register inputs and two or more second register outputs, the two or more second register inputs being respectively coupled to two or more additional LFSM outputs, and the two or more second register outputs being respectively coupled to two or more additional phase shifter inputs.

34. The apparatus of claim 24, wherein the register is a first register and the phase shifter is a first phase shifter, the apparatus further comprising:

a second register comprising two or more second register inputs and two or more second register outputs, the two or more second register inputs being respectively coupled to two or more additional LFSM outputs; and

a second phase shifter comprising two or more second phase shifter inputs and two or more second phase shifter outputs, the two or more second phase shifter inputs being respectively coupled to the two or more second register outputs.

35. One or more computer-readable media storing design data for implementing the apparatus of claim 24.