DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS
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Abstract
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
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Citations
35 Claims
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1-15. -15. (canceled)
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16. A method, comprising:
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inputting compressed test pattern bits; generating decompressed test pattern bits from the compressed test pattern bits; storing the decompressed test pattern bits in one or more registers; and loading scan chains of a circuit-under-test with the decompressed test pattern bits stored in the one or more registers, the loading being performed for two or more scan chain shift cycles such that the decompressed test pattern bits stored in the one or more registers are repeatedly loaded into the scan chain. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. An apparatus, comprising:
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a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs; a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs; and a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification