System and Method for Detecting a Defect

• US 20100138801A1
• Filed: 02/02/2010
• Published: 06/03/2010
• Est. Priority Date: 06/23/2006
• Status: Abandoned Application

• Current Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Morokuma, Hidetoshi, Sutani, Takumichi, MATSUOKA, Ryoichi
• Application Number:
  US12/698,201
• Publication Number:
  US 20100138801A1
• Time in Patent Office: Days
• US Class Current: 716/55
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A system and a method for detecting a defect, capable of extracting a defect occurring depending on finishing accuracy required for circuit operation are provided. The system includes a timing analyzer for extracting a critical path in which a high accuracy is required for a signal transmission operation as compared with other portions based on circuit design data, a critical path extractor for comparing the circuit design data with layout design data on a pattern and for extracting graphical data including the critical path extracted by the timing analyzer, an inspection recipe creator for deciding a portion to be inspected, based on coordinate information on the graphical data including the critical path extracted by the critical path extractor, and an SEM defect review apparatus for acquiring an image of the decided portion to be inspected on a wafer according to an inspection recipe created by the inspection recipe creator.

Claims

1. A system for detecting a defect of a semiconductor in a semiconductor manufacturing process, comprising:

a circuit design data storage unit for storing circuit design data;

a layout design data storage unit for storing layout design data on a pattern;

a timing analyzer for reading the circuit design data from the circuit design data storage unit, and extracting a critical path on a circuit in which a high accuracy is required for a signal transmission operation as compared with other portions;

a critical path extractor for comparing the circuit design data read from the circuit design data storage unit with the layout design data read from the layout design data storage unit, and extracting graphical data including the critical path extracted by the timing analyzer;

a critical path storage unit for storing the graphical data including the critical path extracted by the critical path extractor;

an inspection recipe creator for deciding a to-be-inspected portion, based on coordinate information on the graphical data stored in the critical path storage unit; and

an SEM defect review apparatus for acquiring an image of the to-be-inspected portion on a wafer according to an inspection recipe created by the inspection recipe creator.

2. The system for detecting a defect according to claim 1, further comprising an OPC risky region storage unit for storing an OPC risky region extracted by comparing a predicted pattern shape obtained by performing a light intensity simulation based on an OPC mask pattern, with the layout design data,

wherein the inspection recipe creator decides a portion corresponding to both the graphical data including the critical path and the OPC risky region as the portion to be inspected, based on both information on the critical path read from the critical path storage unit and information on the OPC risky region read from the OPC risky region storage unit.

3. The system for detecting a defect according to claim 2, further comprising a fatal defect storage unit for storing information on a fatal defect extracted by comparing a defect image acquired by the SEM defect detecting apparatus with the layout design data read from the layout design data storage unit,

wherein the inspection recipe creator adds the fatal defect read from the fatal defect storage unit to the portion to be inspected.

4. The system for detecting a defect according to claim 3,

wherein the inspection recipe creator narrows down the fatal defect added to the portion to be inspected to the portion corresponding to the OPC risky region read from the OPC risky region storage unit.

5. The system for detecting a defect according to claim 1, further comprising a fatal defect storage unit for storing information on a fatal defect extracted by comparing a defect image acquired by the SEM defect detecting apparatus with the layout design data read from the layout design data storage unit,

wherein the inspection recipe creator decides a portion corresponding to both the graphical data including the critical path and the fatal defect as the portion to be inspected, based on both the information on the critical path read from the critical path storage unit and the information on the fatal defect read from the fatal defect storage unit.

6. The system for detecting a defect according to claim 5, further comprising an OPC risky region storage unit for storing an OPC risky region extracted by comparing a predicted pattern shape obtained by performing a light intensity simulation based on an OPC mask pattern, with the layout design data,

wherein the inspection recipe creator adds a portion corresponding to both the OPC risky region and the fatal defect as the portion to be inspected, based on both the information on the OPC risky region read from the OPC risky region storage unit and the information on the fatal defect read from the fatal defect storage unit.

7. The system for detecting a defect according to claim 1, further comprising:

a fatal defect storage unit for storing information on a fatal defect extracted by comparing a defect image acquired by the SEM defect detecting apparatus with the layout design data read from the layout design data storage unit; and

an OPC risky region storage unit for storing an OPC risky region extracted by comparing a predicted pattern shape obtained by performing a light intensity simulation based on an OPC mask pattern, with the layout design data,

wherein the inspection recipe creator extracts a portion corresponding to both the OPC risky region and the fatal defect as other portion to be inspected, based on both the information on the OPC risky region read from the OPC risky region storage unit and the information on the fatal defect read from the fatal defect storage unit, and selects a portion to be inspected to be reviewed by the SEM defect review apparatus from both the portion to be inspected, based on the coordinate information on the graphical data stored in the critical path storage unit and the other portion to be inspected.

8. The system for detecting a defect according to claim 1, further comprising:

a fatal defect storage unit for storing information on a fatal defect extracted by comparing a defect image acquired by the SEM defect detecting apparatus with the layout design data read from the layout design data storage unit; and

an OPC risky region storage unit for storing an OPC risky region extracted by comparing a predicted pattern shape obtained by performing a light intensity simulation based on an OPC mask pattern, with the layout design data,

wherein the inspection recipe creator extracts a portion corresponding to both the graphical data including the critical path and the fatal defect as one portion to be inspected, based on both the information on the critical path read from the critical path storage unit and the information on the fatal defect read from the fatal defect storage unit, extracts a portion corresponding to both the OPC risky region and the fatal defect as other portion to be inspected, based on both the information on the OPC risky region read from the OPC risky region storage unit and the information on the fatal defect read from the fatal defect storage unit, and selects a portion to be inspected to be reviewed by the SEM defect review apparatus from the one portion to be inspected and the other portion to be inspected.

9. The system for detecting a defect according to claim 3, further comprising:

an optical defect detecting apparatus for detecting a defect on the wafer by an optical defect detection; and

a CAD filter unit for comparing the defect extracted by the optical defect detecting apparatus with the layout design data read from the layout design data storage unit, and narrowing down positions to an image acquisition position at which the SEM defect review apparatus acquires the image.

10. A method for detecting a defect of a semiconductor in a semiconductor manufacturing process, comprising:

extracting a critical path on a circuit in which a high accuracy is required for a signal transmission operation as compared with other portions based on circuit design data;

comparing the circuit design data with layout design data, and extracting graphical data including the critical path;

deciding a portion to be inspected, based on coordinate information on the extracted graphical data; and

causing an SEM defect review apparatus to acquire an image of the decided portion to be inspected on a wafer.