PRODUCT AUTHENTICATION USING INTEGRATED CIRCUITS

• US 20100140344A1
• Filed: 01/30/2010
• Published: 06/10/2010
• Est. Priority Date: 01/31/2009
• Status: Active Grant

• Current Assignee: Mehrdad Toofan
• Original Assignee: Mehrdad Toofan
• Inventors: Toofan, Mehzad, Toofan, Mehrdad
• Granted Patent: US 8,789,746 B2
• Time in Patent Office: Days
• US Class Current: 235/375
• CPC Class Codes: G06K 19/07703 the interface being visual
• CPC Class Codes: G06K 19/14 the marking being sensed by radiation

Abstract

Authentication of a product could be accomplished by utilizing encryption and decryption engines onboard two integrated circuits namely a DECENC chip and a READER chip. A unique serial number in either an encrypted or un-encrypted format is programmed into eFuses, or OTP devices on board the DECENC chip where this chip is then attached to the product. During the authentication procedure, the encrypted and decrypted serial number on board the DECENC chip is transferred to the READER chip. The READER chip subsequently performs a decryption of the serial number from the first chip if this serial number is in encrypted form or performs an encryption of the serial number from the first chip if this serial number is in un-encrypted form. The READER chip then compares its result of decryption or encryption against the corresponding decrypted or encrypted versions of the serial number received from the DECENC chip. If the results of decryption or encryptions for both chips are the same, then the READER chip signals an authentic product, otherwise it will reject the product as fake.

Claims

1. A method to authenticate a product comprising:

providing a first encoding/decoding chip with the product, wherein the first chip is storing a serial number; and

separately providing a second encoding/decoding chip wherein said authentication method comprises steps of;

a) both the first chip and the second chip decode the serial number from the first chip if this serial number is given as encoded, or encode the serial number from the first chip if the serial number is given as decoded; and

b) the second chip compares its result of encoding or decoding against the result of encoding or decoding from the first chip in step (a)

2. A key in accordance with claim 1, which has been stored on both the first chip and the second chip and is used for encoding or decoding operation by both said chips.

3. The serial number in accordance with claim 1, wherein an opcode or other information is embedded within the serial number which could be used by the first chip or the second chip to carry out the encoding or decoding operation and storing the results.

4. The first chip in accordance with claim 1, which receives its power or clock or data or instructions from the second chip via physical contacts or by wireless methods.

5. The first chip in accordance with claim 1, having a status register or an interrupt mechanism to inform the second chip of completion of a task.

6. The first chip in accordance with claim 1, wherein the desired serial number is programmed onto the first chip using eFUSES, or Poly Fuses, or Metal Fuses, or OTP or similar storage devices.

7. The second chip in accordance with claim 1, whose authenticity is confirmed via phone or a manufacture website using the identification tag that accompanies the second chip.

8. The second chip in accordance with claim 1, embedded in an enclosure equipped with means to display and/or to announce the authenticity and/or information about the nature of a product provided by the second chip.

9. The first chip and the second chip in accordance with claim 1, wherein the two said chips use a variable of the same value to first scramble a key and then using the key to encode or to decode the serial number.

10. The first chip and the second chip in accordance with claim 1, wherein a long term storage bit, such as an eFUSE, is initially programmed to an appropriate logic level on both said chips preventing the chips to operate normally, but subsequently could be activated allowing normal operation of the two chips wherein such activation requires the two chips to receive a predetermined sequence of specific vector patterns.

11. The first chip and the second chip in accordance with claim 1, wherein a specific identification pattern is programmed on each chip that could be used to identify and subsequently determine the health of a particular chip.

12. The first chip in accordance with claim 1, wherein a long term storage bit, such as an eFUSE, is disabled by the second chip to prevent the first chip to function and to operate normally.

13. A method to authenticate a product comprising:

providing a product with a label containing an encoded or decoded serial number and a first encoding/decoding chip storing the same serial number in an encoded or decoding format; and

separately providing a second encoding/decoding chip; and

a verifier entity that carries out the task of verification wherein said authentication method comprises steps of;

a) the verifier requiring the first chip to decode its stored serial number if this serial number is encoded, or to encode its stored serial number if this serial number is decoded;

b) the verifier requiring the second chip to decode the serial number on the label if this serial number is encoded, or to encode the serial number on the label if this serial number is decoded; and

c) comparing the encoding/decoding results in step (a), and (b) by the verifier

14. A key in accordance with claim 13, which has been stored on both the first chip and the second chip and is used for encoding or decoding operation by both said chips.

15. The serial number in accordance with claim 13, wherein an opcode or other information is embedded within the serial number which could be used by the first chip or the second chip to carry out the encoding or decoding operation and storing the results.

16. The first chip and the second chip in accordance with claim 13, which receive their power or clock or data or instructions from the verifier via physical contacts or by wireless methods.

17. The first chip and the second chip in accordance with claim 13, having a status register or an interrupt mechanism to inform the verifier of completion of a task.

18. The first chip in accordance with claim 13, wherein the desired serial number is programmed onto the first chip using eFUSES, or Poly Fuses, or Metal Fuses, or OTP or similar storage devices.

19. The second chip in accordance with claim 13, whose authenticity is confirmed via phone or a manufacture website using the identification tag that accompanies the second chip.

20. The second chip in accordance with claim 13, whose authenticity is confirmed via an identification tag that has been programmed into the second chip, whereby the second chip will be instructed by the verifier to encode or to decode this identification tag and the result would be communicated via phone or a manufacture website for the authentication of the second chip.

21. The verifier in accordance with claim 13 equipped with means to display and/or to announce the authenticity and/or information about the nature of a product provided by the second chip and the first chip.

22. The first chip and the second chip in accordance with claim 13, wherein the two said chips use a variable of the same value to first scramble a key and then using the key to encode or to decode the serial number.

23. The first chip and the second chip in accordance with claim 13, wherein a long term storage bit, such as an eFUSE, is initially programmed to an appropriate logic level on both said chips preventing the chips to operate normally, but subsequently could be activated allowing normal operation of the two chips wherein such activation requires the two chips to receive a predetermined sequence of specific vector patterns.

24. The first chip and the second chip in accordance with claim 13, wherein a specific identification pattern is programmed on each chip that could be used to identify and subsequently determine the health of a particular chip.

25. The first chip in accordance with claim 13, wherein a long term storage bit, such as an eFUSE, is disabled by the verifier to prevent the first chip to function and to operate normally.