SEMICONDUCTOR DEVICE, POLYCRYSTALLINE SEMICONDUCTOR THIN FILM, PROCESS FOR PRODUCING POLYCRYSTALLINE SEMICONDUCTOR THIN FILM, FIELD EFFECT TRANSISTOR, AND PROCESS FOR PRODUCING FIELD EFFECT TRANSISTOR

• US 20100140609A1
• Filed: 03/21/2008
• Published: 06/10/2010
• Est. Priority Date: 03/23/2007
• Status: Active Grant

• Current Assignee: Idemitsu Kosan Company Limited
• Original Assignee: Idemitsu Kosan Company Limited
• Inventors: Inoue, Kazuyoshi, Yano, Koki
• Granted Patent: US 8,158,974 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object of the present invention is to provide a novel semiconductor device which is excellent in stability, uniformity, reproducibility, heat resistance, durability and the like, and can exert excellent transistor properties. The semiconductor device is a thin-film transistor, and this thin-film transistor uses, as an active layer, a polycrystalline oxide semiconductor thin film containing In and two or more metals other than In and having an electron carrier concentration of less than 1×10¹⁸/cm³.

Claims

1. A semiconductor device which uses a crystalline oxide as a semiconductor,

wherein the crystalline oxide contains In and two or more metals other than In, and the crystalline oxide has an electron carrier concentration of less than 1×

10¹⁸/cm³.

2. The semiconductor device according to claim 1, wherein a relation between the number (=) of the atoms of In and the sum (=[X]) of the atoms of the two or more metals other than In contained in the crystalline oxide satisfies a ratio [X]/([X]+[In])=0.0001 to 0.13.

3. The semiconductor device according to claim 1, wherein the crystalline oxide is a crystalline oxide in which when at least the condition of [X]/([X]+[In]) is changed, the electron mobility of the crystalline oxide with respect to the electron carrier concentration thereof increases logarithmically proportionally to the increase of the electron carrier concentration in a predetermined range.

4. The semiconductor device according to claim 1, wherein the two or more metals other than In are a positive bivalent metal and a positive tetravalent metal.

5. The semiconductor device according to claim 4, wherein the positive bivalent metal is at least one element selected from the group consisting of Zn, Mg, Cu, Ni, Co, Ca and Sr,

the positive tetravalent metal is at least one element selected from the group consisting of Sn, Ge, Si, Ti, C, Zr and Hf, and

a relation among the number (=[In]) of the atoms of In, the number (=[M2]) of the atoms of the positive bivalent metal and the number (=[M4]) of the atoms of the positive tetravalent metal contained in the crystalline oxide satisfies the following ratios:

[M2]/([M2]+[M4]+[In])=0.0001 to 0.13; and

[M4]/([M2]+[M4])=0.0001 to 0.3.

6. The semiconductor device according to claim 1, wherein the two or more metals other than In are a positive bivalent metal and a positive trivalent metal.

7. The semiconductor device according to claim 6, wherein the positive bivalent metal is at least one element selected from the group consisting of Zn, Mg, Cu, Ni, Co, Ca and Sr, and

the positive trivalent metal is at least one element selected from the group consisting of Ga, Al, B, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.

8. The semiconductor device according to claim 1, wherein both of the two or more metals other than In are positive bivalent metals.

9. The semiconductor device according to claim 8, wherein the two or more metals other than In are one set selected from the group consisting of Zn and Mg, Zn and Cu, Zn and Co, Zn and Ni, Zn and Ca, and Zn and Sr.

10. The semiconductor device according to claim 1, wherein the concentration of Li, Na and K in the polycrystalline oxide is 1000 ppm or less.

11. The semiconductor device according to claim 1, wherein the crystalline oxide has PAN resistance.

12. The semiconductor device according to claim 1, wherein the crystalline oxide includes, as an impurity, at least one element selected from the group consisting of Ar, Kr, Xe, Ne and N.

13. The semiconductor device according to claim 1, wherein the crystalline oxide is used as an active layer of a thin-film transistor.

14. A polycrystalline semiconductor thin film which contains indium, a positive bivalent element and oxygen,

the thin film having a crystallinity with a locking curve half value width of 1°

or less in an X-ray diffraction method,

wherein crystals are aligned in a predetermined direction.

15. The polycrystalline semiconductor thin film according to claim 14, wherein an X-ray diffraction pattern in the X-ray diffraction method is the pattern of Vicks byte structure, and a diffraction intensity ratio (I(222)/I(400)) between a (222) peak intensity (I(222)) and a (400) peak intensity (I(400)) is I(222)/I(400)<

1.0.

16. The polycrystalline semiconductor thin film according to claim 14, wherein an X-ray diffraction pattern in the X-ray diffraction method is the pattern of Vicks byte structure, and a diffraction intensity ratio (I(222)/I(400)) between a (222) peak intensity (I(222)) and a (400) peak intensity (I(400)) is I(222)/I(400)>

10.

17. The polycrystalline semiconductor thin film according to claim 14, wherein a relation between the number (=[In]) of the atoms of indium and the number (=[X]) of the atoms of the positive bivalent element satisfies a ratio [X]/([X]+[In])=0.0001 to 0.13.

18. The polycrystalline semiconductor thin film according to claim 14, wherein the positive bivalent element is one or more elements selected from the group consisting of zinc, magnesium, copper, cobalt, nickel, calcium and strontium.

19. The polycrystalline semiconductor thin film according to claim 14, which contains a positive tetravalent element in an amount smaller than that of the positive bivalent element.

20. The polycrystalline semiconductor thin film according to claim 14, which is insoluble in a phosphoric acid-based etching solution (PAN), and soluble in an oxalic acid-based etching solution.

21. A process for producing the polycrystalline semiconductor thin film according to claim 14, the process comprising:

a step of forming an amorphous film at a substrate temperature of 150°

C. or less; and

a step of crystallizing the amorphous film at a temperature above 150°

C. and not more than 500°

C. to produce the polycrystalline semiconductor thin film.

22. A field effect transistor which uses, as an active layer, the polycrystalline semiconductor thin film according to claim 14.

23. A process for producing the field effect transistor according to claim 22, the process comprising:

a step of forming an amorphous film as the active layer at a substrate temperature of 150°

C. or less; and

a step of crystallizing the amorphous film at a temperature above 150°

C. and not more than 500°

C. to produce the polycrystalline semiconductor thin film.