FLAT-PANEL DISPLAY SEMICONDUCTOR PROCESS FOR EFFICIENT MANUFACTURING

• US 20100140620A1
• Filed: 12/09/2008
• Published: 06/10/2010
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Majandro LLC (IP Edge LLC)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Lu, Jeng Ping, Ho, Jackson H.
• Granted Patent: US 7,863,115 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.

Claims

1. A method comprising:

forming a poly-last structure for a display panel using an amorphous silicon or amorphous silicon compatible process, the poly-last structure having a channel silicon precursor; and

forming the display panel from the poly-last structure using a polysilicon specific or polysilicon compatible process.

2. The method of claim 1 wherein forming the poly-last structure comprises:

forming a gate region on a substrate for a display panel;

forming source and drain contacts around the gate region;

depositing a doped amorphous silicon layer on the gate region and the source and drain contacts;

patterning source and drain regions on the source and drain contacts; and

depositing the channel silicon precursor on the gate, source and drain regions.

3. The method of claim 2 wherein forming the poly-last structure further comprises:

depositing a passivation layer on the channel silicon precursor;

patterning the passivation layer; and

etching the passivation layer to expose metal bond pads.

4. The method of claim 2 wherein forming the poly-last structure further comprises:

dehydrogenating the doped amorphous silicon layer.

5. The method of claim 2 wherein forming the display panel from the poly-last structure using a polysilicon specific process comprises:

irradiating the channel silicon precursor by a laser.

6. The method of claim 5 wherein irradiating the channel silicon precursor comprises:

irradiating the channel silicon precursor to crystallize silicon under an etched passivation layer.

7. The method of claim 2 wherein forming the poly-last structure further comprises:

scribing the display panel into a predetermined size.

8. The method of claim 2 wherein depositing the doped amorphous silicon layer comprises:

depositing the doped amorphous silicon layer using plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or low pressure chemical vapor deposition (LPCVP).

9. The method of claim 1 wherein depositing the channel silicon precursor comprises:

depositing the channel silicon precursor using plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or low pressure chemical vapor deposition (LPCVP).

10. The method of claim 5 wherein irradiating comprises:

irradiating an island on the channel silicon precursor, the island covering the gate, source and drain regions.

15. The method of claim 10 further comprising:

depositing a passivation layer on the channel silicon precursor;

patterning the passivation layer; and

etching the passivation layer to expose metal bond pads.

11. A method comprising:

forming gate, source, and drain regions on a substrate for a display panel using an amorphous silicon or amorphous silicon compatible process, the gate region corresponding to a bottom gate configuration;

depositing a channel silicon precursor on the gate, source and drain regions in the amorphous silicon or amorphous silicon compatible process; and

irradiating the channel silicon precursor by a laser using a polycrystalline silicon or polycrystalline silicon compatible process.

12. The method of claim 11 wherein forming gate, source, and drain regions comprises:

forming the gate region on a substrate;

forming source and drain contacts around the gate region;

depositing a doped amorphous silicon layer on the gate region and the source and drain contacts; and

patterning the source and drain regions on the source and drain contacts.

13. The method of claim 11 wherein depositing the channel silicon precursor comprises:

depositing the channel silicon precursor using plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or low pressure chemical vapor deposition (LPCVP).

14. The method of claim 12 wherein depositing the doped amorphous silicon layer comprises:

depositing the doped amorphous silicon layer using plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or low pressure chemical vapor deposition (LPCVP).

16. The method of claim 12 further comprising:

dehydrogenating the doped amorphous silicon layer.

17. The method of claim 11 further comprising:

scribing the display panel into a predetermined size.

18. The method of claim 11 wherein irradiating comprises:

irradiating an island on the channel silicon precursor, the island covering the gate, source and drain regions.

19. A structure comprising:

a substrate;

a bottom gate deposited on the substrate;

a dielectric layer deposited on the bottom gate;

doped source and drain regions deposited on the substrate and formed around the bottom gate; and

a channel silicon precursor layer deposited on the patterned doped amorphous silicon layer and the dielectric layer.

20. The structure of claim 19 wherein the substrate is a glass substrate, a flexible metal, or a plastic substrate.

21. The structure of claim 19 wherein the doped amorphous silicon layer has a low concentration of hydrogen atoms.

22. The structure of claim 19 further comprising a passivation layer on the channel silicon precursor layer.

23. A display panel comprising:

a glass substrate; and

a thin film transistor (TFT) array having a plurality of TFTs as pixel switching devices on the glass substrate, each of the TFTs having a bottom gate structure with polycrystalline silicon and data interconnecting lines, the bottom gate structure and the data interconnecting lines being under a silicon layer.

24. The display panel of claim 23 further comprising:

a peripheral driver circuit coupled to the TFT array to drive the pixel switching devices, the peripheral driver circuit having a poly-last architecture.