Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates

• US 20100140693A1
• Filed: 12/11/2009
• Published: 06/10/2010
• Est. Priority Date: 08/08/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hébert, Francois
• Granted Patent: US 8,053,834 B2
• Time in Patent Office: Days
• US Class Current: 257/333
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Claims

1. An inverted field-effect-transistor (iT-FET) semiconductor device comprising:

a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprising a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region wherein said drift region is operated with a floating potential said iT-FET device achieving a self-termination.

2. The iT-FET semiconductor device of claim 1 further comprising:

a top drift region disposed near said top surface of said substrate surrounding an upper portion of said trench and encompassing said drain and contacting said drain link region.

3. The iT-FET semiconductor device of claim 1 wherein:

said low resistivity body-source short structure further comprising a conductive plug extending downwardly from a bottom portion of said trench to said source region.

4. The iT-FET semiconductor device of claim 1 wherein:

said low resistivity body-source short structure further comprising a conductive plug extending downwardly from a bottom portion of said trench through said source region to said body region.

5. The iT-FET semiconductor device of claim 1 wherein:

said low resistivity body-source short structure further comprising a titanium silicide plug extending downwardly from a bottom portion of said trench to said source region.

6. The iT-FET semiconductor device of claim 1 wherein:

said low resistivity body-source short structure further comprising a cobalt silicide plug extending downwardly from a bottom portion of said trench to said source region.

7. The iT-FET semiconductor device of claim 1 wherein:

said low resistivity body-source short structure further comprising a tungsten plug extending downwardly from a bottom portion of said trench to said source region.

8. The iT-FET semiconductor device of claim 1 wherein:

said trench further comprising a thick spacer-oxide layer disposed on an upper portion of said sidewalls for insulating said vertical sidewall gate from said drain to further reduce a gate-drain coupling capacitance.

9. The iT-FET semiconductor device of claim 1 further comprising:

a P+ doped region extending from a bottom of said source region to a P+ substrate.

13. The iT-FET semiconductor device of claim 1 further comprising:

a termination area comprising a trenched gate runner electrically connecting to said vertical sidewall gate for electrically connecting to a gate metal disposed in said termination area.

14. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

15. The iT-FET semiconductor device of claim 1 wherein:

said source and said drain are fully surrounded by said trenched gate for achieving a self-termination configuration.

16. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising an N-channel metal oxide semiconductor field effect transistor (MOSFET) device and said semiconductor substrate is a P-type substrate.

17. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising an N-channel metal oxide semiconductor field effect transistor (MOSFET) device and said semiconductor substrate is a N-type substrate.

18. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising a P channel field effect transistor (FET) device and said semiconductor substrate is a P-type substrate.

19. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising P channel field effect transistor (FET) device and said semiconductor substrate is a N-type substrate.

10. The iT-FET semiconductor device of claim 10 wherein:

said drain further comprising a N+ doped region disposed on said top of said substrate.

11. The iT-FET semiconductor device of claim 10 wherein:

said doped channel region comprising a P doped region disposed in said substrate and surrounding a bottom portion of said trench extending to said source.

12. The iT-FET semiconductor device of claim 10 wherein:

said bottom of said substrate further comprising a P+ doped contact-enhancement zone for enhancing an electrical contact between said source-body short to said source region.

20. A method for manufacturing an iT-FET semiconductor device comprising:

forming a source on a bottom and a drain on a top surface of a semiconductor and forming a trenched gate as a gate layer attached to trench sidewalls for controlling a vertical channel along said trenched gate in said semiconductor substrate.

21. The method of claim 20 further comprising:

forming said trenched gate to fully surround said source and drain all sides whereby said iT-FET device achieving a self-termination.