Trench-Based Power Semiconductor Devices With Increased Breakdown Voltage Characteristics

• US 20100140695A1
• Filed: 03/20/2009
• Published: 06/10/2010
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Yedinak, Joseph A.
• Granted Patent: US 8,304,829 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1-70. -70. (canceled)

71. A semiconductor device comprising:

a first plurality of parallel trenches extending in a semiconductor region, each trench having a shield electrode and a gate electrode vertically stacked therein, the shield and gate electrodes being electrically insulated from each other;

a first pad adapted to receive a first external connection and electrically coupled to the shield electrodes of the first plurality of parallel trenches;

a second pad adapted to receive a second external connection;

an electrical trace electrically coupled to the second pad and to the gate electrode of at least one trench of the first plurality of parallel trenches; and

a second plurality of parallel trenches extending in a semiconductor region and disposed under at least one of the second pad and the electrical trace, each trench of the second plurality having a first electrode disposed therein.

72. The semiconductor device of claim 71, wherein the first electrode of at least one trench of the second plurality of trenches comprises a shield electrode that is electrically coupled to the first pad.

73. The semiconductor device of claim 72, wherein the at least one trench of the second plurality of trenches further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and gate electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

74. The semiconductor device of claim 71, wherein the first electrode of at least one trench of the second plurality of trenches is electrically floating.

75. The semiconductor device of claim 74, wherein the at least one trench of the second plurality of trenches further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and second electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

76. The semiconductor device of claim 71, wherein the first electrode of at least one trench of the second plurality of trenches comprises a shield electrode that is electrically coupled to the first pad;

and

wherein the first electrode of at least another trench of the second plurality of trenches is electrically floating.

77. The semiconductor device of claim 71, further comprising a plurality of mesas of semiconductor material interleaved between the second plurality of parallel trenches, wherein at least one mesa is electrically floating.

78. The semiconductor device of claim 77, wherein the trenches on either side of the at least one mesa that is electrically floating have first electrodes that are electrically floating.

79. The semiconductor device of claim 77, wherein the trenches on either side of the at least one mesa that is electrically floating have first electrodes that are electrically coupled to the first pad.

80. The semiconductor device of claim 71, further comprising:

a first plurality of mesas of semiconductor material interleaved between the first plurality of parallel trenches, the first plurality of mesas having a maximum width; and

a second plurality of mesas of semiconductor material interleaved between the second plurality of parallel trenches, each mesa of the second plurality of mesas having a width that is equal to or less than 1.25 times the maximum width of the first plurality of mesas.

81. The semiconductor device of claim 71, wherein at least one trench of the second plurality of parallel trenches is disposed under the second pad, and wherein at least another trench of the second plurality of trenches is disposed under the electrical trace.

82. The semiconductor device of claim 71, further comprising:

a first plurality of mesas of semiconductor material interleaved between the first plurality of parallel trenches;

a second plurality of mesas of semiconductor material interleaved between the second plurality of parallel trenches;

a plurality of well regions of a first conductivity type disposed in the semiconductor region, each well being disposed in a respective mesa of the second plurality of mesas and between adjacent trenches of the second plurality of parallel trenches.

83. The semiconductor device of claim 82, wherein at least one well region is electrically floating.

84. The semiconductor device of claim 83 wherein the first electrode of a trench disposed adjacent to said at least one well is electrically coupled to the first pad.

85. The semiconductor device of claim 84 wherein said trench disposed adjacent to said at least one well further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and second electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

86. The semiconductor device of claim 83 wherein the first electrode of a trench disposed adjacent to said at least one well is electrically floating.

87. The semiconductor device of claim 83 wherein the first electrode of a first trench disposed adjacent to a first side of said at least one well is electrically coupled to the first pad, and wherein the first electrode of a second trench disposed adjacent to a second side of said at least one well is electrically coupled to the first pad.

88. The semiconductor device of claim 87 wherein said trench disposed adjacent to said at least one well further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and second electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

89. The semiconductor device of claim 83 wherein the first electrode of a first trench disposed adjacent to a first side of said at least one well is electrically floating, and wherein the first electrode of a second trench disposed adjacent to a second side of said at least one well is electrically floating.

90. The semiconductor device of claim 83 wherein the first electrode of a first trench disposed adjacent to a first side of said at least one well is electrically coupled to the first pad, and wherein the first electrode of a second trench disposed adjacent to a second side of said at least one well is electrically floating.

91. The semiconductor device of claim 90 wherein said first trench further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and second electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

92. The semiconductor device of claim 82, wherein the first plurality of mesas have a maximum width, and each mesa of the second plurality of mesas having a width that is equal to or less than 1.25 times the maximum width of the first plurality of mesas.

93. The semiconductor device of claim 82, wherein at least one well region is electrically coupled to the first pad.

94. The semiconductor device of claim 93, wherein the first electrode of a trench disposed adjacent to said at least one well is electrically floating.

95. The semiconductor device of claim 93 wherein the first electrode of a first trench disposed adjacent to a first side of said at least one well is electrically floating, and wherein the first electrode of a second trench disposed adjacent to a second side of said at least one well is electrically floating.

96. The semiconductor device of claim 93 wherein the first electrode of a trench disposed adjacent to said at least one well is electrically coupled to the first pad.

97. The semiconductor device of claim 96 wherein said trench disposed adjacent to said at least one well further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and second electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

98. The semiconductor device of claim 93 wherein the first electrode of a first trench disposed adjacent to a first side of said at least one well is electrically coupled to the first pad, and wherein the first electrode of a second trench disposed adjacent to a second side of said at least one well is electrically coupled to the first pad.

99. The semiconductor device of claim 98 wherein said trench disposed adjacent to said at least one well further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and second electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

100. The semiconductor device of claim 93 wherein the first electrode of a first trench disposed adjacent to a first side of said at least one well is electrically coupled to the first pad, and wherein the first electrode of a second trench disposed adjacent to a second side of said at least one well is electrically floating.

101. The semiconductor device of claim 100 wherein said first trench further comprises a gate electrode vertically stacked over the trench'"'"'s shield electrode, the shield and second electrodes being electrically insulated from each other, the gate electrode being electrically coupled to the second pad.

102. The semiconductor device of claim 96, wherein the first plurality of mesas have a maximum width, and each mesa of the second plurality of mesas having a width that is equal to or less than 1.25 times the maximum width of the first plurality of mesas.