Read-out line

• US 20100141272A1
• Filed: 12/05/2008
• Published: 06/10/2010
• Est. Priority Date: 12/05/2008
• Status: Active Grant

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Nurmi, Juha H-P
• Granted Patent: US 8,138,771 B2
• Time in Patent Office: Days
• US Class Current: 324/654
• CPC Class Codes: G06F 3/045 using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
• CPC Class Codes: H01H 2239/012 Decoding impedances

Abstract

It is disclosed to measure the impedance of a read-out line. The read-out line includes at least two cascaded electrical circuit segments, each electrical circuit segment including two longitudinal arms, wherein one of the longitudinal arms includes an electrical component, and a lateral arm including a switch configured to close in the presence of an object in the vicinity of the switch. The measured impedance of the read-out line can be compared to a preset value corresponding to an allowable value of the impedance of the read-out line.

Claims

1. An apparatus, comprising:

a read-out line comprising at least two cascaded electrical circuit segments, each electrical circuit segment comprising two longitudinal arms, wherein one of the longitudinal arms comprises an electrical component, and a lateral arm comprising a switch configured to close in the presence of an object in the vicinity of the switch,

an analyzer configured to measure the impedance of the read-out line,

a comparator configured to compare the measured is impedance of the read-out line to a preset value corresponding to an allowable value of the impedance of the read-out line.

2. The apparatus of claim 1, characterized in that the electrical component comprises an electrical conductor spanning longitudinal arms of a plurality of electrical circuit segments.

3. The apparatus of claim 1, characterized in that measuring the impedance of the read-out line comprises measuring only one of the inductance, the capacitance and the ohmic resistance of the read-out line.

4. The apparatus of claim 1, characterized in that it comprises a plurality of read-out lines.

5. The apparatus of claim 4, characterized in that the analyzer is one of:

configured to measure the impedances of the plurality of read-out lines sequentially,

configured to measure the impedance of the plurality of read-out lines parallelly.

6. The apparatus of claim 4, characterized in that the comparator is one of:

configured to compare the measured impedances of the read-out lines to preset values, each preset value corresponding to an allowable value of the impedance of the respective read-out line, sequentially,

configured to compare the measured impedances of the read-out lines to preset values, each preset value corresponding to an allowable value of the impedance of the respective read-out line, parallelly.

7. The apparatus of claim 4, characterized in that the read-out lines of the plurality of read-out lines have a similar configuration.

8. The apparatus of claim 4, characterized in that the read-out lines are arranged in parallel.

9. The apparatus of claim 1, characterized in that the read-out line forms part of a user interface.

10. The apparatus of claim 9, characterized in that that the user-interface is a touch screen.

11. The apparatus of claim 1, characterized in that it comprises a processor configured to assign a coordinate pair to at least one closed switch.

12. The apparatus of claim 11, characterized in that assigning a coordinate pair to a combination of closed switches involves selecting a read-out line of a plurality of read-out lines.

13. The apparatus of claim 12, characterized in that assigning a coordinate pair to a combination of closed switches involves selecting the pair of read-out lines of all read-out lines comprising a closed switch that has a maximum distance to each other.

14. The apparatus of claim 11, characterized in that assigning a coordinate pair to a combination of closed switches involves averaging coordinates of a plurality of switches.

15. The apparatus of claim 1, characterized in that it comprises a processor configured to assign a plurality of coordinate pairs to a combination of closed switches and in that the analyzer is configured to measure the impedances of a pair of read-out lines from opposed ends of the read-out lines.

16. The apparatus of claim 12, characterized in that assigning a coordinate pair to a combination of closed switches involves selecting two read-out lines of a plurality of read-out lines, each selected read-out line having a closed switch, wherein for each selected read-out line an adjacent read-out line does not have a closed switch or the distance of the closed switch of the adjacent read-out line along an axis extending in the direction of the read-out lines to the closed switch of the selected read-out line exceeds a preset limit.

17. An apparatus, comprising:

a read-out line comprising at least two cascaded electrical circuit segments, each electrical circuit segment comprising two longitudinal arms, wherein one of the longitudinal arms comprises an electrical component, and a lateral arm comprising means for closing in the presence of means for inputting in their vicinity,

means for measuring the impedance of the read-out line,

means for comparing the measured impedance of the read-out line to a preset value corresponding to an allowable value of the impedance of the read-out line.

18. A method, comprising:

measuring the impedance of a read-out line, the read-out line comprising at least two cascaded electrical circuit segments, each electrical circuit segment comprising two longitudinal arms, wherein one of the longitudinal arms comprises an electrical component, and a lateral arm comprising a switch configured to close in the presence of an object in the vicinity of the switch,

comparing the measured impedance of the read-out line to a preset value corresponding to an allowable value of the impedance of the read-out line.

19. A computer-readable medium having a computer program stored thereon, the computer program comprising instructions operable to cause a processor to:

control an analyzer to measure the impedance of a read-out line, the read-out line comprising at least two cascaded electrical circuit segments each electrical circuit segment comprising two longitudinal arms, wherein one of the longitudinal arms comprises an electrical component, and a lateral arm comprising a switch configured to close in the presence of an object in the vicinity of the switch,

to compare the measured impedance of the read-out line to a preset value corresponding to an allowable value of the impedance of the read-out line.