Power management and control apparatus for resetting a latched protection in a power supply unit

• US 20100141320A1
• Filed: 12/09/2009
• Published: 06/10/2010
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: Lin, Tzu-Chen, Huang, Pei-Lun
• Granted Patent: US 8,004,333 B2
• Time in Patent Office: Days
• US Class Current: 327/198
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03K 17/082 by feedback from the output to the control circuit
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals

Abstract

A controller which has functions of remote control, multiple protection and PWM inside. The controller can shut down and latch the converter, when a failure happens (such as under voltage and over voltage of output, and over power protection). But, under-voltage and over-power protection will also happen when Vin is decreased by AC interruption or Vin source is removed. This invention is to provide a method to reset the latch protection by detecting Vin and Vo voltage.

Claims

1. A power management and control apparatus for resetting a latched protection in a power supply unit, comprising:

a reset unit for detecting an input voltage and an output voltage to output a reset control signal to reset the latch protection;

at least one failure protection unit for outputting a corresponding protection control signal when a failure happens; and

a first logic circuit which receives the signals outputted from the reset unit and the at least one failure protection unit to output a control signal to control the power latch;

wherein the first logic circuit latches the power supply unit by latching the control signal in OFF state when a failure happens and the input voltage is not lower than a predefined threshold value; and

the first logic circuit will reset the latched protection of power when a failure happens and the input voltage is lower than a predefined threshold value.

2. A power management and control apparatus according to claim 1, wherein the at least one failure protection unit is selected from the group consisting of:

an under-voltage protection unit (UVP), an over-voltage protection unit (OVP), and an over-power protection unit (OPP).

3. A power, management and control apparatus according to claim 1, wherein the reset unit comprising:

a first comparator for detecting the input voltage and comparing it to a reference voltage to output a first compare signal;

a second comparator for detecting the output voltage and comparing it to the reference voltage to output a second compare signal; and

a second logic circuit for outputting the reset control signal based on the protection control signal of the at least one failure protection unit, the first compare signal, and the second compare signal.

4. A power management and control apparatus according to claim 3, wherein the second logic circuit comprising:

a first logic gate which receives the protection control signal of the at least one failure protection unit and the first compare signal to output a first output signal;

a flip-flop which receives the first output signal to output a second output signal; and

a second logic gate which receives the first compare signal and the second compare signal to output the reset control signal.

5. A power management and control apparatus according to claim 4, wherein the received protection control signal is an UVP signal or an OPP signal.

6. A power management and control apparatus according to claim 1, wherein the first logic circuit comprising:

a third logic gate which receives an ON/OFF signal to output a third output signal;

a fourth logic gate which receives the signal of the at least one failure protection unit to output a fourth output signal;

a fifth logic gate which receives the reset control signal of the reset unit to output a fifth output signal;

a flip-flop which receives the third output signal, the fourth output signal, and the fifth output signal to output a seventh output signal; and

a sixth logic gate which receives the seventh output signal and the ON/OFF signal to output a sixth output signal to control the power latch.