AMPLIFIER WITH PROGRAMMABLE OFF VOLTAGE

• US 20100141337A1
• Filed: 12/10/2008
• Published: 06/10/2010
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chen, Minghui
• Granted Patent: US 8,514,015 B2
• Time in Patent Office: Days
• US Class Current: 330/124.R
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2203/21178 Power transistors are made by coupling a plurality of single transistors in parallel
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated

Abstract

An amplifier with multiple stages and having improved reliability is described. The multiple amplifier stages are coupled in parallel and include at least one switchable amplifier stage. Each switchable amplifier stage may be operated in an on state or an off state and includes a gain transistor and a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and is disabled in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state and is disabled based on an off voltage in the off state. The off voltage may be greater than zero volts or may have one of multiple possible values. The off voltage may be generated based on an output signal level, e.g., may be set to different values for different ranges of output signal level.

Claims

1. An apparatus comprising:

multiple amplifier stages to amplify an input signal and provide an output signal, the multiple amplifier stages being coupled in parallel and comprising at least one switchable amplifier stage, each switchable amplifier stage being operated in an on state or an off state and comprising

a gain transistor to amplify the input signal and provide an amplified signal in the on state and to not amplify the input signal in the off state, and

a cascode transistor coupled to the gain transistor and to buffer the amplified signal and provide the output signal in the on state, the cascode transistor being disabled based on an off voltage in the off state, the off voltage being greater than zero volts or having one of multiple possible values.

2. The apparatus of claim 1, further comprising:

a voltage generator to generate the off voltage based on an output signal level.

3. The apparatus of claim 2, the multiple possible values of the off voltage being associated with multiple ranges of output signal level, and the off voltage being set to a value determined based on a range covering the output signal level.

4. The apparatus of claim 1, further comprising:

a voltage generator to receive at least one control signal for the at least one switchable amplifier stage and to generate the off voltage based on the at least one control signal, each control signal setting a corresponding switchable amplifier stage to the on state or the off state.

5. The apparatus of claim 1, further comprising:

a voltage generator comprising multiple resistors coupled in series and providing the multiple possible values of the off voltage.

6. The apparatus of claim 1, the multiple possible values of the off voltage comprising zero volts.

7. The apparatus of claim 1, the off voltage being less than a threshold voltage of the cascode transistor.

8. The apparatus of claim 1, each switchable amplifier stage further comprising

an inverter or a buffer to receive a control signal for the switchable amplifier stage and to provide a control voltage for the cascode transistor, the inverter or buffer being coupled between an on voltage to enable the cascode transistor and the off voltage to disable the cascode transistor.

9. The apparatus of claim 8, each switchable amplifier stage further comprising

a resistor coupled between an output of the inverter or buffer and a gate of the cascode transistor, and

a capacitor coupled between the gate of the cascode transistor and circuit ground.

10. The apparatus of claim 8, further comprising

a voltage generator to receive the output signal and generate the on voltage for the inverter or buffer in each switchable amplifier stage.

11. The apparatus of claim 1, further comprising:

an inductor coupled between outputs of the multiple amplifier stages and a supply voltage, the output signal having a voltage swing below and above the supply voltage.

12. The apparatus of claim 1, at least one of the multiple amplifier stages being enabled when the apparatus is transmitting.

13. The apparatus of claim 1, the at least one switchable amplifier stage being enabled or disabled to obtain a target output signal level.

14. An integrated circuit comprising:

multiple amplifier stages to amplify an input signal and provide an output signal, the multiple amplifier stages being coupled in parallel and comprising at least one switchable amplifier stage, each switchable amplifier stage being operated in an on state or an off state and comprising

a gain transistor to amplify the input signal and provide an amplified signal in the on state and to not amplify the input signal in the off state, and

a cascode transistor coupled to the gain transistor and to buffer the amplified signal and provide the output signal in the on state, the cascode transistor being disabled based on an off voltage in the off state, the off voltage being greater than zero volts or having one of multiple possible values.

15. The integrated circuit of claim 14, further comprising:

a voltage generator to generate the off voltage based on an output signal level.

16. The integrated circuit of claim 14, the gain transistor and the cascode transistor comprising N-channel metal oxide semiconductor (NMOS) transistors or P-channel metal oxide semiconductor (PMOS) transistors.

17. A method comprising:

amplifying an input signal with a gain transistor to obtain an amplified signal in an on state;

buffering the amplified signal with a cascode transistor and providing an output signal in the on state; and

disabling the cascode transistor with an off voltage in an off state, the off voltage being greater than zero volts or having one of multiple possible values.

18. The method of claim 17, further comprising:

generating the off voltage based on an output signal level.

19. The method of claim 18, the generating the off voltage comprising

setting the off voltage to zero volts if the output signal level is below a threshold, and

setting the off voltage to a value greater than zero volts if the output signal level is greater than the threshold.

20. The method of claim 17, further comprising:

generating an on voltage based on the output signal; and

setting a control voltage for the cascode transistor to the off voltage in the off state or to the on voltage in the on state.

21. The method of claim 17, further comprising:

enabling at least one of multiple amplifier stages coupled in parallel, each amplifier stage comprising the gain transistor and the cascode transistor; and

disabling the cascode transistor in each disabled amplifier stage with the off voltage.

22. The method of claim 21, further comprising:

generating the off voltage based on which at least one amplifier stage is enabled among the multiple amplifier stages.

23. An apparatus comprising:

means for amplifying an input signal to obtain an amplified signal in an on state;

means for buffering the amplified signal and providing an output signal in the on state; and

means for disabling the means for buffering with an off voltage in an off state, the off voltage being greater than zero volts or having one of multiple possible values.

24. The apparatus of claim 23, further comprising:

means for generating the off voltage based on an output signal level.

25. The apparatus of claim 24, the means for generating the off voltage comprising

means for setting the off voltage to zero volts if the output signal level is below a threshold, and

means for setting the off voltage to a value greater than zero volts if the output signal level is greater than the threshold.