SHIFT REGISTER

• US 20100141641A1
• Filed: 05/15/2008
• Published: 06/10/2010
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Furuta, Shige, Murakami, Yuhichiroh, Sasaki, Yasushi, Shimizu, Shinsaku
• Granted Patent: US 8,269,713 B2
• Time in Patent Office: Days
• US Class Current: 345/213
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET

Abstract

In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Claims

1. A shift register having a configuration in that unit circuits each configured with transistors of an identical conduction type are cascaded, and operating based on two-phase clock signals whose on-level periods do not overlap with each other, wherein

the unit circuit includes:

an output control transistor having a first conduction terminal supplied with one of the clock signals, and a second conduction terminal connected to an output terminal;

a precharge circuit for applying an on-voltage to a control terminal of the output control transistor during a period that an input signal is at an on-level;

a reset signal generation circuit for generating a reset signal which turns into the on-level in a normal state, by use of the two-phase clock signals, and changing the reset signal to an off-level when the input signal turns into the on-level; and

a discharge circuit for applying an off-voltage to the control terminal of the output control transistor during a period that the reset signal is at the on-level.

2. The shift register according to claim 1, wherein

the unit circuit further includes an output reset circuit for applying the off-voltage to the output terminal during the period that the reset signal is at the on-level.

3. The shift register according to claim 1, wherein

the reset signal generation circuit includes:

a first transistor having a control terminal supplied with one of the clock signals, and a first conduction terminal applied with the on-voltage;

a second transistor having a control terminal supplied with the remaining clock signal, and a first conduction terminal connected to a second conduction terminal of the first transistor; and

a third transistor having a control terminal supplied with the input signal, a first conduction terminal connected to a second conduction terminal of the second transistor, and a second conduction terminal applied with the off-voltage, and

the reset signal is output from a connection point between the second and third transistors.

4. The shift register according to claim 1, wherein

the unit circuit further includes an initialization circuit for fixing the reset signal at the on-level in accordance with an initialization signal.

5. The shift register according to claim 1, wherein

the unit circuit further includes an additional output control transistor having a control terminal and a first conduction terminal connected as in those of the output control transistor, and a second conduction terminal connected to an additional output terminal, and

an output signal from the output terminal is output externally, and an output signal from the additional output terminal is supplied to the subsequent unit circuit.

6. The shift register according to claim 5, wherein

the unit circuit further includes an additional output reset circuit for applying the off-voltage to the additional output terminal during the period that the reset signal is at the on-level.

7. A display device comprising:

a plurality of pixel circuits arranged in a two dimensional manner; and

a drive circuit including the shift register according to claim 1.

8. A display device comprising:

a plurality of pixel circuits arranged in a two dimensional manner; and

a drive circuit including the shift register according to claim 2.

9. A display device comprising:

a plurality of pixel circuits arranged in a two dimensional manner; and

a drive circuit including the shift register according to claim 3.

10. A display device comprising:

a plurality of pixel circuits arranged in a two dimensional manner; and

a drive circuit including the shift register according to claim 4.

11. A display device comprising:

a plurality of pixel circuits arranged in a two dimensional manner; and

a drive circuit including the shift register according to claim 5.

12. A display device comprising:

a plurality of pixel circuits arranged in a two dimensional manner; and

a drive circuit including the shift register according to claim 6.