ANALOG MULTIPLEXER CONFIGURED TO REDUCE KICKBACK PERTURBATION IN IMAGE SENSOR READOUT

• US 20100141822A1
• Filed: 12/08/2008
• Published: 06/10/2010
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Xue, Song
• Granted Patent: US 8,184,184 B2
• Time in Patent Office: Days
• US Class Current: 348/332
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An analog multiplexer is configured to multiplex a plurality of input analog signal channels into a single output analog signal channel. The analog multiplexer comprises a plurality of input sampling circuits associated with respective ones of the input analog signal channels and an amplifier having an input controllably connectable in turn to each of the input sampling circuits. The analog multiplexer is further configured to connect at least a given one of the input analog signal channels to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier. The predetermined time is less than a full clock cycle of a sampling clock of the amplifier. The analog multiplexer may be implemented in readout circuitry coupled to a pixel array in an image sensor.

Claims

1. An analog multiplexer for multiplexing a plurality of input analog signal channels into a single output analog signal channel, the multiplexer comprising:

a plurality of input sampling circuits associated with respective ones of the input analog signal channels; and

an amplifier having an input controllably connectable in turn to each of the input sampling circuits;

wherein the analog multiplexer is further configured to connect at least a given one of the input analog signal channels to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier; and

wherein the predetermined time is less than a fill clock cycle of a sampling clock of the amplifier.

2. The multiplexer of claim 1 wherein the amplifier is operated at a sampling speed which is greater than a sampling speed of the input sampling circuits.

3. The multiplexer of claim 2 wherein the sampling speed of the amplifier is at least twice the sampling speed of the input sampling circuits.

4. The multiplexer of claim 2 wherein the predetermined time is approximately one half of the fill clock cycle of the sampling clock of the amplifier.

5. The multiplexer of claim 1 wherein at least one of the input analog signal channels comprises a programmable gain amplifier.

6. The multiplexer of claim 1 wherein the sampling element comprises a sampling capacitor and a first plate of the sampling capacitor is connected to the given input analog signal channel at the predetermined time prior to a second plate of the sampling capacitor being connected to the input of the amplifier.

7. The multiplexer of claim 1 wherein the given input sampling circuit comprises positive and negative inputs coupled to respective positive and negative differential signal lines of the corresponding input analog signal channel and the amplifier comprises a differential amplifier having positive and negative inputs.

8. The multiplexer of claim 7 wherein the multiplexer is configured to connect the positive and negative inputs of the given input sampling circuit to respective first plates of respective first and second sampling capacitors at the predetermined time prior to connecting respective second plates of the first and second sampling capacitors to the respective positive and negative inputs of the differential amplifier.

9. The multiplexer of claim 7 wherein the given input sampling circuit comprises:

a positive signal path having a first switch coupled between the positive input of the input sampling circuit and a first plate of a first sampling capacitor;

a negative signal path having a second switch coupled between the negative input of the input sampling circuit and a first plate of a second sampling capacitor;

third and fourth switches coupled between respective second plates of the first and second sampling capacitors and a common mode voltage reference; and

fifth and sixth switches arranged in series with the respective first and second switches and the respective first and second sampling capacitors in the respective positive and negative signal paths and coupled between the respective second plates of the first and second sampling capacitors and the respective positive and negative inputs of the differential amplifier.

10. The multiplexer of claim 9 wherein the given input sampling circuit further comprises:

seventh and eighth switches coupled between the respective first plates of the first and second sampling capacitors and respective upper and lower voltage references; and

a ninth switch coupled between the respective first plates of the first and second sampling capacitors.

11. The multiplexer of claim 10 wherein in a given phase of operation of the multiplexer the third, fourth and ninth switches are closed, and the first, second, fifth, sixth, seventh and eighth switches are open, such that the positive and negative inputs of the input sampling circuit are disconnected from the respective first plates of the respective first and second sampling capacitors, the first plates of the first and second sampling capacitors are connected to one another, the second plates of the first and second sampling capacitors are connected to the common mode voltage reference, and the second plates of the first and second sampling capacitors are disconnected from the respective positive and negative inputs of the differential amplifier.

12. The multiplexer of claim 10 wherein in a given phase of operation of the multiplexer the first, second, third and fourth switches are closed, and the fifth, sixth, seventh, eighth and ninth switches are open, such that the positive and negative inputs of the input sampling circuit are connected to the respective first plates of the respective first and second sampling capacitors, and the second plates of the first and second sampling capacitors are disconnected from the respective positive and negative inputs of the differential amplifier and connected to the common mode voltage reference.

13. The multiplexer of claim 10 wherein in a given phase of operation of the multiplexer the first, second, fifth and sixth switches are closed and the third, fourth, seventh, eighth and ninth switches are open, such that the positive and negative inputs of the input sampling circuit are connected to the respective first plates of the respective first and second sampling capacitors, and the second plates of the first and second sampling capacitors are connected to the respective positive and negative inputs of the differential amplifier.

14. The multiplexer of claim 10 wherein in a given phase of operation of the multiplexer the fifth, sixth, seventh and eighth switches are closed and the first, second, third, fourth and ninth switches are open, such that the positive and negative inputs of the input sampling circuit are disconnected from the respective first plates of the respective first and second sampling capacitors, the first plates of the respective first and second sampling capacitors are connected to the respective upper and lower voltage references, and the second plates of the first and second sampling capacitors are connected to the respective positive and negative inputs of the differential amplifier.

15. The multiplexer of claim 1 wherein the amplifier is configured to provide output reference offset cancellation.

16. An analog multiplexing method comprising the steps of:

receiving a plurality of input analog signal channels; and

combining the plurality of input analog signal channels into a single output analog signal channel in an analog multiplexer comprising a plurality of input sampling circuits associated with respective ones of the input analog signal channels and an amplifier having an input controllably connectable in turn to each of the input sampling circuits;

wherein in conjunction with the combining step at least a given one of the input analog signal channels is connected to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier; and

wherein the predetermined time is less than a full clock cycle of a sampling clock of the amplifier.

17. The method of claim 16 wherein in conjunction with the combining step positive and negative inputs of the given input sampling circuit are connected to respective first plates of respective first and second sampling capacitors at the predetermined time prior to connecting respective second plates of the first and second sampling capacitors to respective positive and negative inputs of the amplifier.

18. An image sensor comprising:

a pixel array; and

readout circuitry coupled to the pixel array;

the readout circuitry comprising an analog multiplexer configured to multiplex a plurality of input analog signal channels into a single output analog signal channel;

the analog multiplexer comprising a plurality of input sampling circuits associated with respective ones of the input analog signal channels and an amplifier having an input controllably connectable in turn to each of the input sampling circuits,

wherein the analog multiplexer is further configured to connect at least a given one of the input analog signal channels to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier; and

wherein the predetermined time is less than a full clock cycle of a sampling clock of the amplifier.

19. The image sensor of claim 18 wherein the readout circuitry further comprises an analog-to-digital converter and the amplifier is implemented in an input sampling stage of the analog-to-digital converter.

20. A digital imaging device comprising the image sensor of claim 19.