PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY

• US 20100142268A1
• Filed: 02/09/2010
• Published: 06/10/2010
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 8,050,096 B2
• Time in Patent Office: Days
• US Class Current: 365/185.20
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level.

Claims

1. A method of programming a selected memory cell of an array of memory cells to a desired programming state, the method comprising:

adjusting the desired programming state to an adjusted programming state, wherein the adjusted programming state comprises a programming state where the selected memory cell achieves the desired programming state in response to coupling effects resulting from a subsequent programming operation performed on a first memory cell adjacent to the selected memory cell.

2. The method of claim 1, wherein a subsequent programming operation performed on the first memory cell adjacent to the selected memory cell further comprises a subsequent programming operation performed on the first memory cell where the first memory cell is adjacent the selected memory cell by a row of the array of memory cells.

3. The method of claim 1, wherein a subsequent programming operation performed on the first memory cell adjacent to the selected memory cell further comprises a subsequent programming operation performed on the first memory cell where the first memory cell is adjacent the selected memory cell by a column of the array of memory cells.

4. The method of claim 1, wherein adjusting the desired programming state to an adjusted programming state further comprises, adjusting the desired programming state to an adjusted programming state where the selected memory cell achieves the desired programming state due to coupling effects resulting from a subsequent programming operation performed on a second memory cell adjacent to the selected memory cell.

5. The method of claim 4, further comprising programming the selected memory cell to the adjusted programming state prior to programming the second memory cell adjacent to the selected memory cell.

6. The method of claim 5, wherein the subsequent programming of the first memory cell and the second memory cells further comprises the subsequent programming of the first memory cell and the second memory cell as part of a programming operation of a page of memory cells.

7. A method of programming memory cells of a memory array, the method comprising:

receiving first data to be written in a first memory cell;

receiving second data to be written in a second memory cell, wherein the second memory cell is adjacent the first memory cell and where the first and the second data each corresponds to one of a plurality of programming levels to be programmed in the first and the second memory cells;

determining a plurality of adjustment amounts, wherein each adjustment amount of the plurality of adjustment amounts corresponds to one of the plurality of programming levels;

adjusting the first data by an adjustment amount corresponding to a programming level of the received second data; and

programming the first memory cell with the adjusted first data prior to programming the second memory cell.

8. The method of claim 7, wherein determining a plurality of adjustment amounts further comprises determining a plurality of adjustment amounts where each adjustment amount compensates for coupling effects resulting from a programming operation of a particular programming level to be performed on the second memory cell of the memory array.

9. The method of claim 7, wherein adjusting the first data further comprises adjusting the first data by one of the plurality of adjustment amounts such that the first memory cell achieves a programming level corresponding to the received first data upon completion of subsequently programming the second memory cell with the second data.

10. A method of compensating for programming interference effects in a memory device comprising an array of memory cells, the method comprising:

characterizing a first coupling ratio between a first plurality of memory cells and a second plurality of memory cells of the array of memory cells where the first plurality of memory cells are adjacent the second plurality of memory cells in the array of memory cells;

receiving first data to be programmed into the first plurality of memory cells;

receiving second data to be programmed into the second plurality of memory cells;

adjusting the first data to be programmed into each of the first plurality of memory cells by an amount dependent upon the second data to be programmed into an adjacent memory cell of the second plurality of memory cells and further dependent upon the first characterized coupling ratio; and

programming the first plurality of memory cells with the adjusted first data prior to programming the second plurality of memory cells.

11. The method of claim 10, further comprising characterizing a second coupling ratio between the first plurality of memory cells and a third plurality of memory cells of the array where the first plurality of memory cells are adjacent the third plurality of memory cells in the array of memory cells, and receiving third data to be programmed into the third plurality of memory cells.

12. The method of claim 11, wherein adjusting the first data to be programmed into each of the first plurality of memory cells further comprises adjusting the first data to be programmed into each of the first plurality of memory cells where adjusting the first data is further dependent upon the second characterized coupling ratio and the third data to be programmed in each adjacent memory cell of the third plurality of memory cells.

13. The method of claim 12, wherein programming the first plurality of memory cells with the adjusted first data further comprises programming the first plurality of memory cells with the adjusted first data prior to programming the third plurality of memory cells.

14. The method of claim 10, wherein characterizing a first coupling ratio between a first plurality of memory cells and a second plurality of memory cells of the array of memory cells further comprises characterizing a first coupling ratio between a first plurality of memory cells and a second plurality of memory cells of the array of memory cells during manufacturing of the memory device.

15. The method of claim 10, wherein characterizing a first coupling ratio between a first plurality of memory cells and a second plurality of memory cells further comprises characterizing a first coupling ratio between a first plurality of memory cells and a second plurality of memory cells where the first and the second pluralities of memory cells comprise multi-level memory cells.

16. A method of programming memory cells of an array of memory cells, the method comprising:

receiving a first data value to be programmed into a first memory cell, the first data value corresponding to a first range of threshold voltages;

receiving a second data value to be programmed into a second memory cell, the second data value having a corresponding range of threshold voltages, and where the second memory cell is adjacent to the first memory cell; and

programming the first memory cell to a first adjusted threshold voltage outside of the first range of threshold voltages to compensate for interference by the subsequent programming of the second data value into the second memory cell.

17. The method of claim 16, further comprising receiving a third data value to be programmed into a third memory cell the third data value having a corresponding range of threshold voltages, and where the third memory cell is adjacent to the second memory cell.

18. The method of claim 17, further comprising programming the second memory cell to a second adjusted threshold voltage outside of the second range of threshold voltages to compensate for interference by the subsequent programming of the third data value into the third memory cell.

19. The method of claim 18, further comprising receiving a fourth data value to be programmed into a fourth memory cell the fourth data value having a corresponding range of threshold voltages, and where the fourth memory cell is adjacent to the first and the third memory cells.

20. The method of claim 19, further comprising programming the third memory cell to a third adjusted threshold voltage outside of the third range of threshold voltages to compensate for interference by the subsequent programming of the fourth data value into the fourth memory cell.