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PAGE BUFFER CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE PAGE BUFFER CIRCUIT, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE

  • US 20100142277A1
  • Filed: 06/29/2009
  • Published: 06/10/2010
  • Est. Priority Date: 12/08/2008
  • Status: Active Grant
First Claim
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1. A page buffer circuit, comprising:

  • a bit line selection unit configured to select a bit line coupled to memory cells;

    a latch unit, comprising a plurality of latch circuits coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells; and

    a bit line control unit coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

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