PAGE BUFFER CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE PAGE BUFFER CIRCUIT, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE

• US 20100142277A1
• Filed: 06/29/2009
• Published: 06/10/2010
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Yang, Chang Won, Koo, Cheul Hee, Won, Sam Kyu
• Granted Patent: US 7,898,876 B2
• Time in Patent Office: Days
• US Class Current: 365/185.120
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

Claims

1. A page buffer circuit, comprising:

a bit line selection unit configured to select a bit line coupled to memory cells;

a latch unit, comprising a plurality of latch circuits coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells; and

a bit line control unit coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

2. The page buffer circuit of claim 1, wherein the bit line control unit comprises:

voltage charge means for charging the voltage of the selected bit line;

a first switching element coupled between the sense node and the voltage charge means and configured to connect the sense node and the voltage charge means in response to the charge control signal;

a second switching element coupled to an input terminal of a power source voltage; and

a third switching element configured to, when the second switching element transfers the power source voltage to the sense node in response to the transfer control signal, change the degree to which the third switching element is turned-on according to a voltage level charged at the voltage charge means, thus changing a voltage level transferred to the sense node.

3. A nonvolatile memory device, comprising:

a memory cell array comprising a number of memory blocks each including memory cells for storing data, the memory cells being coupled by a bit line and a word line;

a page buffer unit, comprising page buffers coupled to the bit line and configured to include a plurality of latch circuits for latching data to be programmed into the memory cells or storing data from the memory cells, wherein each of the page buffers comprises a bit line control unit configured to temporarily charge a voltage of a bit line varying according to a program degree of memory cells when a program verification operation is performed and to provide the bit line with the charged voltage when a program operation for the bit line is performed; and

a control unit configured to control a program, read, or erase operation, charge a voltage of a bit line according to a verification result to the page buffer when a program verification operation is performed using a double verification method, and apply the bit line with the voltage charged at the page buffer when a program operation is performed.

4. The nonvolatile memory device of claim 3, wherein each of the page buffers of the page buffer unit comprises:

a bit line selection unit configured to select the bit line;

a latch unit, comprising a plurality of latch circuits coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells; and

the bit line control unit coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

5. The nonvolatile memory device of claim 4, wherein the bit line control unit comprises:

voltage charge means for charging the voltage of the selected bit line;

a first switching element coupled between the sense node and the voltage charge means and configured to connect the sense node and the voltage charge means in response to the charge control signal;

a second switching element coupled to an input terminal of a power source voltage; and

a third switching element configured to, when the second switching element transfers the power source voltage to the sense node in response to the transfer control signal, change the degree to which the third switching element is turned-on according to a voltage level charged at the voltage charge means, thus changing a voltage level transferred to the sense node.

6. A method of operating a nonvolatile memory device, the method comprising:

a first program step of performing a program operation using a first program voltage;

a first verification step of performing a first verification operation on selected memory cells using a first verification voltage and temporarily charging a voltage of a bit line coupled to the selected memory cells;

a second verification step of performing a second verification operation using a second verification voltage higher than the first verification voltage;

a bit line voltage change step of, if a result of the second verification operation is not a pass, precharging the bit line in proportion to the temporarily charged voltage; and

a second program step of performing a program operation using a second program voltage higher than the first program voltage by as much as a step voltage.

7. The method of claim 6, further comprising, after the second program step, performing the first verification operation and the second verification operation, and if a result of the second verification operation is not a pass, performing a third program operation using a third program voltage higher than the second program voltage by as much as the step voltage after the bit line voltage change step.

8. The method of claim 7, wherein, if a result of the second verification operation is a pass, a program operation is terminated.

9. A page buffer circuit, comprising:

a bit line selection unit configured to select a bit line coupled to memory cells;

a latch unit configured to latch data to be programmed into the memory cells or store data from the memory cells through a sense node; and

a bit line control unit configured to charge a voltage of the selected bit line in response to a charge control signal when a program verification operation is performed, and when a result of the program verification operation is a fail, re-execute the program verification operation by supplying the selected bit line with the charged voltage in response to a transfer control signal.

10. The page buffer circuit of claim 9, wherein the bit line control unit comprises:

voltage charge means for charging the voltage of the selected bit line;

a first switching element coupled between the sense node and the voltage charge means and configured to connect the sense node and the voltage charge means in response to the charge control signal;

a second switching element coupled to an input terminal of a power source voltage; and

a third switching element configured to, when the second switching element transfers the power source voltage to the sense node in response to the transfer control signal, change the degree to which the third switching element is turned-on according to a voltage level charged at the voltage charge means, thus changing a voltage level transferred to the sense node.