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Digitally-Controllable Delay for Sense Amplifier

  • US 20100142303A1
  • Filed: 12/08/2008
  • Published: 06/10/2010
  • Est. Priority Date: 12/08/2008
  • Status: Active Grant
First Claim
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1. A circuit for use with a magnetic resistance-based memory, the circuit comprising:

  • a sense amplifier having a first input, a second input, and an enable input;

    a first amplifier coupled to an output of a cell of the magnetic resistance-based memory;

    a second amplifier coupled to a reference of the output of the cell; and

    a third digitally-controllable amplifier coupled to a tracking circuit cell that includes at least one element that is similar to the cell of the magnetic resistance-based memory,wherein the first input is coupled to the first amplifier, the second input is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit.

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