Method of Forming Stacked Dies
First Claim
1. A method of fabricating a stacked integrated circuit (IC) semiconductor die comprising:
- forming one or more recesses in a first semiconductor wafer;
filling the one or more recesses with conducting material to form one or more through-silicon vias in the first semiconductor wafer;
forming one or more bonding contacts on a front-side of the first semiconductor wafer;
attaching the front-side of the first semiconductor wafer to a carrier, exposing a back-side of the first semiconductor wafer;
thinning the back-side of the first semiconductor wafer until the one or more through-silicon vias are exposed and slightly protrude the back-side; and
aligning and bonding the one or more through-silicon vias with corresponding one or more bonding contacts on one or more bonding surfaces on a second semiconductor die or wafer.
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Accused Products
Abstract
The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.
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Citations
20 Claims
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1. A method of fabricating a stacked integrated circuit (IC) semiconductor die comprising:
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forming one or more recesses in a first semiconductor wafer; filling the one or more recesses with conducting material to form one or more through-silicon vias in the first semiconductor wafer; forming one or more bonding contacts on a front-side of the first semiconductor wafer; attaching the front-side of the first semiconductor wafer to a carrier, exposing a back-side of the first semiconductor wafer; thinning the back-side of the first semiconductor wafer until the one or more through-silicon vias are exposed and slightly protrude the back-side; and aligning and bonding the one or more through-silicon vias with corresponding one or more bonding contacts on one or more bonding surfaces on a second semiconductor die or wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a stacked integrated circuit (IC) semiconductor die comprising:
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providing a first semiconductor wafer having one or more through-silicon vias formed in a substrate; attaching a front-side surface of the first semiconductor wafer to a carrier, exposing a back-side of the first semiconductor wafer; thinning the back-side of the first semiconductor wafer until the one or more through-silicon vias are exposed and slightly protrude the back-side; forming one or more first bonding contacts in a metallization insulator layer over the thinned back-side of the first semiconductor wafer, the one or more first bonding contacts being electrically coupled to the one or more through-silicon vias; providing a second semiconductor work-piece having one or more second bonding contacts on a bonding surface of the second semiconductor die; and aligning and bonding the one or more first bonding contacts on the first semiconductor wafer to the corresponding one or more second bonding contacts on the second semiconductor work-piece. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification